Basic LCD knowledge

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1 LCD Controller

The function of the LCD controller is to generate display drive signals and drive the LCD display. Different controllers can support display of passive Array Display (STN) and Active Array Display (TFT), including monochrome and color, one-way refresh mode and two-way refresh mode. You only need to read and write a series of registers to complete configuration and display control.

1.1 Overview

The display data generated by the processor is first stored in the frame buffer of the external memory. The data is loaded to a Buffer Queue of first-in-first-out (FIFO) by the LCD DMA controller in sequence. When one-way refresh mode is adopted, only one DMA channel is working and a FIFO buffer queue is corresponding. When the two-way refresh mode is used, both DMA channels work and correspond to two FIFO buffer queues at the same time.

The data in the frame buffer is called the frame buffer data, which corresponds to the color values of pixels on the screen. The frame buffer data can be the color value after compression or the original color value, depending on the display mode selected by the LCD controller. In color mode, the original color value is a 16-bit RGB color value, including Red 5, Green 6, and Blue 5 (because human eyes are sensitive to Green, so Green occupies one more place. A 16-Bit Data describes the color of a pixel on the screen. The color values of the compressed encoding can be described with a small number of BITs. Reducing the color data volume of each pixel can increase the display refresh rate and reduce the amount of data transmitted. However, the color value of the compressed encoding must be explained by the color Palette (Palette) to describe the true color value of the pixel.

1. color palette

The color palette is not used when the original color value is used, that is, a 16-bit description of a pixel point. The monochrome color palette is an 8-bit wide data structure with a 256 entrance. It is equivalent to uint8 palette [256] and can represent a gray scale of 256. The color palette is a 16-bit wide data structure with a 256 entrance. It is equivalent to uint16 palette [256] and can represent a pseudo color of 256 colors. The number of color descriptors per pixel after compression determines the number of descriptive colors: one pixel can access two colors in the color palette, you can access four colors in the color palette at 2 bits per pixel. You can access 16 colors in the palette at 4 bits per pixel. You can access 256 colors in the palette at 8 bits per pixel.

2. Refresh Mode

The STN display adopts a passive refresh mode. Sometimes, to improve the LCD color performance, you can refresh the pixels of each screen multiple times and use a time-mixed color. This method is also called transient jitter.

The TFT display adopts the active refresh mode without instantaneous jitter.

The numbers of LCD data output pins are also different for different display modes, and the number of data pins used in the bidirectional refresh mode must be twice that of the unidirectional refresh mode, this is because the bidirectional refresh mode refreshes both the upper half and lower half of the screen.

3. Control clock

(1) pixel clock (pixel clock)

Corresponding to the ll_pclk pin on the chip, the LCD display is used to control the control clock signal of the Line Shift Register (Line Shift Register) in which the display data enters the row. The higher the frequency, the higher the row resolution. In passive refresh mode, only the clock starts to flip when the valid display data arrives. In the active refresh mode, the clock is continuously flipped, and the effective message of data is determined by the AC bias signal.

(2) line clock)

The lclk corresponds to the on-Chip Pin, And the LCD display is used to indicate the clock signal refreshed by a line of pixels on the screen. When the row clock signal is generated, it indicates that the display will start to refresh the next row of pixels. The controller will transfer the display data stored in the next row in the row display displacement register to the display, add the row position counter to 1. In the active refresh mode, the row clock signal is also called the horizontal synchronous signal.

(3) frame clock)

Corresponding to the on-Chip Pin l_fclk, the LCD display is used to indicate that the entire screen is refreshed, and there is a new frame waiting for the display of the clock signal. When the signal arrives, the monitor resets the row position counter to the first line of the screen (closest to the top of the screen ). In active refresh mode, frame clock signals are also called vertical synchronous signals.

4. Features

The LCD controller has the following features.

N display mode:

Supports one-way or two-way refresh;

A maximum of 256 levels of gray scale (8-bit compression encoding) can be displayed in passive monochrome mode );

A maximum of 65536 colors can be displayed in active color mode (16-bit instantaneous jitter );

A maximum of 65536 colors can be displayed in active color mode (16 BITs do not use instantaneous jitter );

Supports passive 256-color pseudo-color one-way refresh mode;

Ø supports passive 256-color pseudo-color two-way refresh mode.

The maximum resolution of N is 1024 × 1024 pixels. We recommend that you set the maximum resolution to 640 × 480 pixels;

N supports an external Ram color palette with a 256-entry 16-Bit Width data (it can be automatically loaded at the beginning of each frame );

N compression encoding pixels Support 1, 2, 4, and 8 bits;

N programmable pixel clock, frequency range: kHz ~ 83 MHz (100 MHz/512 to 166 MHz/2 );

N has a dual DMA channel (one channel is used to transmit the color palette and one-way refresh data, and the other channel is used to transmit the data refreshed on the lower half of the screen in two-way refresh mode ).

1.2 LCD controller registers

The LCD controller has four control registers, ten DMA registers, one Status Register, and one ram color board. All registers must be accessed by a 32-bit address, and read/write operations on the undefined Register address space should not be performed, which leads to unexpected errors.

1. Control Register

The following functions can be used to set the corresponding bits of these registers:

N start and stop the LCD controller;

N sets the height and width of the LCD screen;

N specifies whether one-way or two-way screen brush is used;

N specifies whether the color or grayscale or pure black/white display is used;

N sets the level valid value of the control pin;

N sets the frame clock, row clock, pixel clock, and AC bias pin signal frequency;

N sets the amount of empty data inserted before and after the screen display data (row data and frame data) (coordinates the minimum data transfer volume of the screen size );

N can enable multiple types of Interrupt shielding.

(1) zero control register (lccr0)

When the ENB of lccr0 is set to 1, the LCD controller starts. After the controller is started, no changes can be made to other control spaces. This requires special attention during programming, and the stop of the LCD controller is controlled by control registers.

N LCD output queue overflow interrupt shielding control bit (Oum)

When Oum = 0, the off-flow interrupt is enabled. When the ou status bit in the lcsr is set to 1, an off-flow interrupt request is generated. The Interrupt Controller responds to the request to complete error handling. When Oum = 1, The underflow interruption is blocked.

N quickly disable the interrupt shielding control bit (qdm)

When QDM = 0, the interruption is quickly stopped and enabled. When the QD status bit in LCSR is set to 1, an LCD quickly closes the interrupt request and the interrupt controller responds to the request. QDM = 1 is blocked. Quick Close is generally used in sleep mode.

N LCD closed control bit (DIS)

When DIS = 1, the LCD controller stops reading new frame data from the cache after reading the data of the current frame. After the display of the current frame is complete, the LCD controller is disabled.

N active/passive display mode selection position (PAS)

This one is used to control the display mode, active or passive display mode. When PAS is set to 0, the passive mode is selected. When PAS = 1, the active mode is selected.

N unidirectional/bidirectional refresh mode selection bit (SDS)

If SDS is set to 0, one-way refreshing is performed. If SDS is set to 1, two-way refreshing is performed. In active mode, SDS must be 0.

Table7-2 considerations

N color/monochrome mode selection bit (CMS)

When CMS is set to 0, the color mode is selected, and the color data of the corresponding color palette is 16 bits. When CMS is set to 1, the monochrome mode is selected, and the color data of the corresponding color palette is 8 bits (up to 256 levels of gray scale ).

N LCD start control bit (ENB)

When ENB is set to 0, all LCD pins are used as general IO ports; When ENB is set to 1, the LCD controller is enabled.

(2) 1 control register (LCCR1)

The values of the four fields in this register are used to control the sequence of display related clock signals in LCD rows. They are the default counter values respectively.

N-row front null pixel clock beats (BLW)

The number of empty pixel clock beats to wait before a row of pixels is displayed. BLW can generate 1 ~ The waiting period of the 256-pixel clock, corresponding to the BLW value 0 ~ 255.

Number of null pixel clock beats after n rows (ELW)

Like BLW, it is the number of empty pixel clock beats to wait after a row of pixels is displayed.

N horizontal synchronous signal pulse width (HSW)

The HSW value specifies the pulse width of the downlink clock signal in active or passive mode. When the clock signal of each row is valid, the HSW value is assigned to a six-digit counter. When each pixel clock arrives, the counter minus 1. When the counter is 0, the row clock signal is invalid. The HSW value ranges from 0 ~ 63, which can be 1 ~ The pulse width between 64.

Number of partitions in n rows (PPL)

PPL can describe 0 ~ Value in the range of 1023, which specifies the number of pixels in a line on the screen (1 ~ 1024 pixels ). We recommend that you set the value to a maximum of 640 pixels. In different pixel description modes, PPL values also have different requirements: PPL + 1 must be a multiple of 32 for one-bit description per pixel, PPL + 1 must be a multiple of 16 when two characters are described per pixel. PPL + 1 must be a multiple of 8 when four characters are described per pixel, PPL + 1 must be a multiple of 4 for each pixel's 8-bit description. PPL + 1 must be a multiple of 2 for each pixel's 16-bit description. When the PPL and the actual screen's row pixel values are not matched, empty pixels will be introduced and BLW or ELW will be used.

(3) control register 2 (LCCR2)

Similar to LCCR1, the values of the four fields in this register are used to control the time sequence of displaying related clock signals in the upper frame of the LCD.

(4) number of front-end empty-line clock beats (BFW)

It is used only in Active Display Mode, indicating the number of idle-line clock beats to be waited before a new frame is displayed. BLW can generate 0 ~ The wait cycle of the 255-row clock. If BLW is set to 0, no wait is performed.

(5) Number of idle-line clock beats after frames (EFW)

It is used only in Active Display Mode. Similar to BFW, it is the number of idle-line clock beats to wait after a frame pixel display ends.

(6) pulse width of the Vertical Synchronous signal (VSW)

The vsw value specifies the pulse width of the frame clock signal in active or passive mode. In active mode, when the clock signal of each frame is valid, the vsw value is assigned to a six-digit counter. When the clock of each row arrives, the counter is reduced by 1. When the counter is 0, the frame signal is invalid. In passive mode, vsw is used to provide an extra empty-line clock. When the current frame is displayed and ends, the vsw value is assigned to a six-digit counter to count the empty-clock signal, when the counter is 0, the next frame starts (BFW and EFW still exist ). The vsw value ranges from 0 ~ 63, which can be 1 ~ The pulse width between 64 or the number of extra null clocks.

(7) number of screens (LPP)

LPP can describe 0 ~ Value in the range of 1023, which specifies the number of rows on the screen (1 ~ 1024 rows ).

(8) Description per pixel (BPP)

The number of digits that a pixel color value occupies in memory. In the compression encoding mode of 1, 2, 4, and 8 bits per pixel, before these pixels are displayed, their color palette must be loaded to obtain the true color value. Bpp = 0b000, 1-bit description per pixel. Bpp = 0b001, 2-bit description per pixel. Bpp = 0b010, 4-bit description per pixel. Bpp = 0b011, 8-bit description per pixel. Bpp = 0b100, 16-bit description per pixel. Other reserved values are used for future extension.

(9) pixel clock edge validity selection (PCP)

When PCP is set to 0, the rising edge of l_pclk is valid, and the data on the LCD data pin is sampled. When PCP is set to 1, the l_pclk descent edge is valid, and the data of the lcdlcd data pin is sampled.

(10) Selection of level effectiveness of horizontal synchronous signals)

If the value of MK is 0, the high level of l_lclk is valid. If the value of MK is 1, the low level of l_lclk is valid. In passive mode, the horizontal synchronous signal is the row clock signal.

(11) Selection of Vertical Synchronous signal level validity (VSP)

When VSP is set to 0, the High-Level Rochelle fclk is valid. When VSP is set to 1, the low-level Rochelle fclk is valid.

(12) pixel clock Division (PCD)

The PCD value ranges from 0 ~ Between 255, representing 1 ~ The value of 256 is multiplied by 2 ). The final pixel clock frequency is between LCLK/2 and LCLK/512. The LCLK frequency is equal to the clock frequency of the LCD memory controller, generally between MHz and MHz ~ Between 166MHz.

2. Status Register (LCSR)

The status bit of the Status Register can indicate:

N overflow and underflow errors of the FIFO buffer queue;

N DMA bus error;

N when the DMA controller starts and ends the transmission of one frame of data;

N when the last frame before the LCD is closed is displayed.

(1) frame end status bit (EOF)

When the DMA controller acquires a frame of display data from the memory and the frame descriptor in the data contains a flag indicating the end of the frame, then EOF = 1, if the EFM blocking bit in LCCR0 is not set, an EOF interrupt request is generated.

(2) Fast LCD shutdown status bit (QD)

When QD = 1, QDM = 0, a fast shutdown interrupt will occur, which will force the LCD controller to stop and immediately stop the driver of the LCD pin. Quick shutdown can be used in LCD sleep mode.

(3) Output FIFO underflow (OU)

If the output FIFO is empty, OU = 1 when the LCD data pin continues to get the display data from the FIFO. If OUM = 0, an output FIFO overflow interruption occurs.

(4) On-screen input FIFO overflow status bit (IUU)

If the on-screen input FIFO is empty, IUU = 1 will continue when the LCD controller's pixel decoder tries to obtain compressed encoding data from FIFO. If IUM is set to 0, an input FIFO overflow is interrupted.

(5) input the FIFO overflow status bit on the off-screen (IUL)

Used only when two-way refresh mode is selected (SDS = 1, IUL = 1 when the pixel decoder of the LCD controller continues to obtain compressed encoding data from the FIFO. If IUM is set to 0, an input FIFO overflow is interrupted.

(6) Bus Error status bit (BER)

When the DMA transmission controller encounters a system bus error, the BER is 1. For example, when the DMA controller attempts to access a reserved or nonexistent bucket. When an error occurs, the DMA controller stops working until the valid address space is loaded into the FDADRx register.

(7) frame start position (SOF)

When the DMA controller obtains a new frame Descriptor and contains a flag indicating the start of the frame, SOF = 1. If the SFM shielding bit in LCCR0 is not set, a sof interrupt request will be generated.

(8) LDD)

When DIS = 1, when the LCD controller reads all data of the current frame, the LCD controller is disabled after the last pixel data of the current frame is sent to the LCD data pin, LDD is set to 1. If LDM is set to 0, a request to close the service will be generated. This status bit is set by hardware, but its clearing is done by software.

(9) other registers

In addition to the main registers described above, there are also some registers that will be used. For example, LCD dma command register (ld420x), LCD controller interrupt ID register (LIIDR), instantaneous jitter RGB color offset register (TRGBR), and instantaneous jitter control register (CRS.

1.3 LCD controller operation

1. Frame cache and bus bandwidth

The cache size required to store a display frame data can be calculated using the following formula:

FrameBufferSize = (BitPerPixel 'lines' (Pixels + n)/8 (in bytes)

Here, BitPerPixel indicates the number of bit bits required for a pixel, for example, BitPerPixel = 8 for a gray scale of 256 and BitPerPixel = 16 for a 64 K color. Lines is equal to the number of Lines displayed on the screen. Pixels is the number of Pixels in a row on the screen, and n is the number of inserted empty Pixels (for display control ).

In two-way refresh mode, the two DMA pipelines have the same frame buffer size. Therefore, Lines are half the screen size when calculating the frame buffer in the next pipeline in this mode.

The bandwidth of the data transmission bus of the LCD controller can be calculated according to the following formula:

N unidirectional

BusBandwidth = (FrameBufferSize + PaletteSize) 'refreshrate

N bidirectional

BusBandwidth = (FrameBufferSize * 2 + PaletteSize) 'refreshrate

The PaletteSize is the size of the color palette, the size of the color palette is 256 '8bit = 256 byte, and the color palette is 256 '16 = 512 byte. RefreshRate is the screen update rate.

In two-way mode, the DMA pipeline responsible for the upper half screen is responsible for transmitting the display data of the Palette and the upper half screen, while the DMA pipeline responsible for the lower half screen is only the display data of the lower half screen, therefore, PaleteSize is not multiplied by 2 in the formula of Bidirectional mode.

2. Timing of Passive Mode

The time sequence of the initial mode is 4-1 to 4-3, as shown in Figure 4-3.

 

ENB-LCD enabling Signal	MK-set the polarity of Horizontal synchronization
0-LCD prohibited	0-the row clock is highly effective and low is invalid.
1-LCD enabling	1-The row clock is low and valid, and the row clock is high.
VSP-Vertical synchronization polarity settings	PCP-pixel clock polarity settings
0-the frame clock is highly effective, and low is invalid.	0-sample pixel data on the rising edge of the clock
1-low and invalid frame clock	1-sample pixel data along the descent of the clock
When PCP is set to 0, the L_PCLK waveform is reversed, but the time sequence is the same.
VSW = Vertical Synchronous signal pulse width-1
HSW = horizontal synchronous signal (row clock) Pulse Width-1
BLW = number of start row pixel clock waits-1
ELW = number of pixel clock waits for the end row-1

Figure 4-1 passive mode frame startup sequence

 

ENB-LCD enabling Signal	MK-set the polarity of Horizontal synchronization
0-LCD prohibited	0-the row clock is highly effective and low is invalid.
1-LCD enabling	1-The row clock is low and valid, and the row clock is high.
VSP-Vertical synchronization polarity settings	PCP-pixel clock polarity settings
0-the frame clock is highly effective, and low is invalid.	0-sample pixel data on the rising edge of the clock
1-low and invalid frame clock	1-sample pixel data along the descent of the clock
When PCP is set to 0, the L_PCLK waveform is reversed, but the time sequence is the same.
VSW = Vertical Synchronous signal pulse width-1
HSW = horizontal synchronous signal (row clock) Pulse Width-1
BLW = number of start row pixel clock waits-1
ELW = number of pixel clock waits for the end row-1
PPL = pixel-1 per line
LPP = number of rows per screen-1

Figure 4-2 passive mode frame end sequence

PCP-pixel clock polarity settings

0-sample pixel data on the rising edge of the clock

1-sample pixel data along the descent of the clock

When PCP is set to 0, the L_PCLK waveform is reversed, but the time sequence is the same.

Figure 4-3 passive mode pixel clock and data pin timing

3. Timing of Active Mode

The time sequence of the active mode is 4-4 and the figure 4-4 shows.

4. LCD startup

After configuring the corresponding General I/O pins to the LCD controller and setting the correct color palette, the memory address of the frame descriptor, and some necessary registers other than LCCR0, after the ENB control bit of LCCR0 is set, the LCD controller starts.

ENB-LCD enabling Signal	MK-set the polarity of Horizontal synchronization
0-LCD prohibited	0-the row clock is highly effective and low is invalid.
1-LCD enabling	1-The row clock is low and valid, and the row clock is high.
VSP-Vertical synchronization polarity settings	PCP-pixel clock polarity settings
0-the frame clock is highly effective, and low is invalid.	0-sample pixel data on the rising edge of the clock
1-low and invalid frame clock	1-sample pixel data along the descent of the clock
When PCP is set to 0, the L_PCLK waveform is reversed, but the time sequence is the same.
VSW = Vertical Synchronous signal pulse width-1
HSW = horizontal synchronous signal (row clock) Pulse Width-1
BFW = number of start frame Horizontal synchronization clock waits
BLW = number of start row pixel clock waits-1
ELW = number of pixel clock waits for the end row-1
PPL = pixel-1 per line

Figure 4-4 Timing of Active Mode

 

PCP-pixel clock polarity settings

0-sample pixel data on the rising edge of the clock

1-sample pixel data along the descent of the clock

When PCP is set to 0, the L_PCLK waveform is reversed, but the time sequence is the same.

Figure 4-5 active pattern clock and data pin timing

The pseudocode is as follows:

# Define LCCR0_ADDRESS 0x44000000 // LCCR0 address

# Define LCCR0 (* (volatile unsigned int *) LCCR0_ADDRESS ))

# Define LCD _ENB 0x00000001 // The position of ENB in LCCR0

LCCR0 = LCCR0 | LCD _ENB; // set ENB

5. LCD stopped

(1) normal stop

We recommend that you stop the LCD controller. This operation is completed by setting the DIS control bit of LCCR0. After the LCD controller loads the final frame data to be displayed, the LCSR LDD status bit is automatically set by the hardware, and The ENB bit in LCCR0 is also cleared by the hardware.

The pseudocode is as follows:

# Define LCCR0_ADDRESS 0x44000000 // LCCR0 address

# Define LCCR0 (* (volatile unsigned int *) LCCR0_ADDRESS ))

# Define LCSR_ADDRESS 0x44000038 // address of LCSR

# Define LCSR (* (volatile unsigned int *) LCSR_ADDRESS ))

# Define LCD _DIS 0x00000400 // location of DIS in LCCR0

# Define LCD _LDD 0x00000001 // location of LDD in LCSR

LCCR0 = LCCR0 | LCD _DIS; // The LCD _DIS position in LCCR0

While (! (LCSR & LCD _LDD); // wait for the hardware to set the LDD

LCSR = LCSR &(~ LCD _LDD); // The software clears the LCD _LDD bit for the next use

(2) Quick Stop

You can directly clear the ENB control bit of LCCR0 to quickly stop the operation. After the ENB is cleared, the QD status bit of the LCSR will be set to an interrupt, And the LCD controller will immediately stop loading all the frame data after the interrupt response, stop the driver of the LCD controller on the LCD pins. When the battery power is insufficient, the CPU uses the Quick Stop Mode to save important data.

The pseudocode is as follows:

# Define LCCR0_ADDRESS 0x44000000 // LCCR0 address

# Define LCCR0 (* (volatile unsigned int *) LCCR0_ADDRESS ))

# Define LCD _ENB 0x00000001 // The position of ENB in LCCR0

LCCR0 = LCCR0 &(~ LCD _ENB); // clear the ENB bit