Chapter 3.1 Proficiency in HDL language: VERILOG,VHDL-Preface

I can't wait to write these things myself. This chapter is essential for the development of hardware. Besides, we have to develop a CPU. ~ ~ often see someone released what Verilog code god Horse, feel very cow. In fact, you can also learn to. Manual up, follow along.

In the previous chapters, we learned to design a variety of line diagrams, with levels of abstraction ranging from high to low, functional block level, logic gate level, MOS tube level, cabling and VLSI design at a later stage. So when you are doing the finite state machine (FSM) exercise, it is not necessary to draw a line map, it is the door level diagram is very laborious, not difficult but error prone. Then a slightly more complex state machine, light is prone to hundreds of CMOS, not to mention the computer God Horse (think of the CPU integrated hundreds of millions of MOS ... ）。 So people design CAD tools (using computers to help design software) to automate the design and optimization of logic circuits. Of course, the computer still listens to the person to tell it how to do, so everybody pulls together to design the hardware description Language (hdl--hardware description language). Now the Universal has VHDL and Verilog. Of course, we first Master one can be, another nature will be taught. Verilog is used in this series because it is particularly concise and is one of the IEEE standards. And VHDL is the U.S. Defense Agency (presumably defense) developed, we may feel very uncomfortable to use, especially those who have programming experience.

Let's have a hands-on touch first. Download the Xilinx Ise simulator and synplify Pro from synplicity to go. I use the old version. Synplify Pro from synplicity has image compositing, which is the code written with Xilinx Ise, which is put in to give the corresponding logic gate diagram. Give the Xilinx ise download address: HTTP://APP.HUSTONLINE.NET/MAJOR/DETAIL/1.

Everyone first down, the file is relatively large, I also try to use the new version ~ a day of class, take a break and go swimming, night back to continue to update

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