Computer composition principle-system bus and computer composition principle

Computer composition principle-system bus and computer composition principle
1. Basic concepts of Bus 1. Why should I use a bus?

Von noriman divides computers into five parts: memory, memory, controller, input device, and output device. Many channels are required to connect these devices.

2. Bus

Bus-connected information transmission lines of each component are the transmission media shared by each component.

3. Transmission of Information on the bus

Serial: one-digit signal is transmitted at a time.

Parallel: short transmission distance,

4. computer example of bus structure 4.1 single bus structure diagram 4.2 CPU-oriented Dual Bus Structure Diagram 4.3 memory-centric dubus structure diagram 2. Bus Classification 1. in-chip Bus: Bus Inside the chip 2. system Bus: Information Transmission Lines between various computer components

• Data Bus: two-way connection with machine and storage
• Address Bus: one-way connection with storage address and I/O address
• Control Bus: With inbound and outbound traffic

3. Communication bus:

Used for communication between computer systems or between computer systems and other systems (such as control instruments and mobile communications)

• Serial Communication Bus
• Parallel Communication Bus

3. Bus characteristics and performance indicators 1. physical implementation of the Bus 2. Bus Characteristics

• Mechanical Characteristics: size, shape, number of pins, and order
• Electrical Properties: Transmission Direction and valid level range
• Features: functions of each transmission line (address, Data, control)
• Time Characteristics: timing relationship of Signals

3. Bus performance indicators

• Bus width: number of data lines
• Standard Transfer Rate: Maximum number of bytes transmitted per second (MBps)
• Clock Synchronization/Asynchronization: Synchronous and non-synchronous
• Bus multiplexing: address line and data line multiplexing
• Signal line number: The sum of address line, data line, and control line
• Bus Control Mode: burst, automatic, arbitration, logic, and count
• Other indicators: Load Capacity

4. Bus Standard

Bus Standard	Data Line	Bus clock	Bandwidth
ISA	16	8 MHz (independent)	16 MBps
EISA	32	8 MHz (independent)	33 MBps
VESA (VL-BUS)	32	32 MHz (CPU)	132 MBps
PCI	32 64	33 MHz (independent) 66 MHz (independent)	132 MBps 528 MBps
AGP	32	66.7 MHz (standalone) 13 MHz (independent)	266 MBps 533 MBps
RS-232	Serial Communication Bus Standard	Standard Interface between data terminal device (Computer) and data communication device (modem)
USB	Serial Interface Bus Standard	Common unshielded twisted pair wires Shielded twisted pair wires Highest	1.5 Mbps (USB1.0) 12 Mbps (USB2.0) 480 Mbps (USB3.0)

4. Bus Structure 1. Single Bus Structure 2. Multi-bus structure

Dual-bus structure, three-bus structure, I/O bus, and four-bus structure

5. Bus Control 1. Bus Optimization Control

Basic Concepts

• Master device (module): has control over the bus
• Slave Device (module): responds to bus commands sent from the master device
• Bus Optimization Control
  • Centralized:
  • Chain Query
  • Counter timed Query
  • Independent Request Method
  • Distributed

2. Bus Communication Control

Objective: To resolve the coordination and cooperation issues between the communication parties

Bus transmission cycle:

• Application allocation phase: Main module application, bus arbitration decision
• Addressing stage: the master module provides the address and command to the slave module.
• Transmission Phase: data exchange between the master module and slave module
• End stage: the main module cancels related messages.

Four bus communication methods

• Synchronous communication: data is controlled on a unified time scale.
• Asynchronous Communication
• Semi-synchronous communication
• Separate Communication

(1) synchronous data input (4) semi-synchronous communication (synchronous and asynchronous)

Synchronous sender sends signals at the front of the system clock
The receiver uses the system clock to determine and identify the background.

Asynchronous mode allows harmonious operation of modules at different speeds
Add a "WAIT" response signal WAIT

The three types of communication have the following commonalities:

One bus transmission cycle (taking input data as an example)

• Main module Sending address and command (occupying the bus)
• Prepare data from the module (no bus occupation)
• Send data from the module to the main module (occupying the bus)

(5) separate communication

Fully tap the potential of the system bus at every moment

One bus transmission cycle:

• Sub-cycle 1: The main module applies for occupying the bus. after use, the right to use the bus is waived.
• Subcycle 2: Apply for bus occupation from the module and send various information to the bus

Features