Cross-clock domain design "three"--data synchronization

This paper introduces the basic method of pulse synchronization used in the project, its basic function is to remove a single clock width pulse from a clock domain, and then establish another pulse in the new clock domain, but in practical application, it is often not only pulse signal, data bus, Both the address bus and the control bus may be transmitted across domains. The handshake protocol, RAM, and FIFO are the most basic methods, but these methods are not necessarily the best approach if FPGA resources become a key factor. Here is another method--toggle (already used in the project), suitable for fast clock domain to slow clock domain transfer data.

If data is a clock domain Clka (20MHz), which needs to be synchronized to the clock domain clkb (80MHz), we can generate a toggle signal in clock domain A, divide the Clka by 2, and then synchronize the toggle signal to CLKB, It also captures data at the rising and falling edges of the toggle, which ensures that the rising and falling edges of the toggle signal collect two adjacent data, and the data is not lost. The Verilog HDL of the method is as follows:

Module Datasync (
Input Rst_n,
Input Clka,
Input ClkB,
input [7:0] Data,

Output reg [7:0] Data_sync
);

Reg Toggle;
Reg Toggle_d;
Reg TOGGLE_DD;
Reg TOGGLE_DDD;
Wire Toggle_edge;

Always @ (Posedge Clka or Negedge rst_n)
if (!rst_n)
Toggle <= 1 ' b0;
Else
Toggle <= ~toggle;

Always @ (Posedge ClkB or Negedge rst_n)
if (!rst_n)
Begin
Toggle_d <= 1 ' b0;
TOGGLE_DD <= 1 ' b0;
TOGGLE_DDD <= 1 ' b0;
End
Else
Begin
Toggle_d <= Toggle;
Toggle_dd <= toggle_d;
TOGGLE_DDD <= Toggle_dd;
End

Always @ (Posedge ClkB or Negedge rst_n)
if (!rst_n)
Data_sync <= 8 ' h00;
else if (toggle_dd ^ toggle_ddd)
Data_sync <= Data;

Endmodule
The application of this method is limited, and the specific problem is analyzed in practical application.

Cross-clock domain design "three"--data synchronization