Design of divider based on Verilog (half-integer, fractional-divide: lower)

Half-integer divider: The counter is triggered by the rising edge, so when the count is N-1, the Count trigger is flipped, the clock's falling edge changes to the rising edge, so the count value is 0, so every time the n+0.5-frequency clock is generated, the trigger clock is flipped once. , using XOR gate and 2-way module design pulse deduction circuit, pulse deduction is the input frequency and 2 output difference or results.

ModuleFenpin (clk,rst_n,clk_out);inputCLK;inputRst_n;Outputclk_out;RegClk_out2; Wireclk_out1;Reg[1:0] CNT;RegFB_CLK; always@(PosedgeClk_out2,Negedgerst_n)begin if(!rst_n) FB_CLK<=0;ElseFB_CLK<=~FB_CLK;End always@(PosedgeCLK_OUT1,Negedgerst_n)begin if(!rst_n)beginCNT<=0; Clk_out2<=0;EndElse if(cnt==2)beginCNT<=0; Clk_out2<=1;EndElsebeginCNT<=cnt+1'B1;clk_out2<=0;EndEndXORXor1 (CLK_OUT1,CLK,FB_CLK); WireClk_out_r;AssignClk_out_r= (cnt==1) ?1'b0:1'B1;AssignClk_out=clk_out2 |Clk_out_r;Endmodule

Design of divider based on Verilog (half-integer, fractional-divide: lower)