Design of Embedded Intelligent Nodes Based on Lonworks Bus

Design of Embedded Intelligent Nodes Based on Lonworks Bus

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Source: carefree electronic development network Author: Wang zhenchen, Yan xubin, Wang Shuxian

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1 Preface

LonWorks fieldbus is a local operating network launched by Echelon in the United States. It has excellent performance such as uniformity, openness, interoperability and support for multiple communication media. It is one of the most popular fieldbus today. However, due to the relatively weak application processing capability of the LonWorks control node's core Neuron Chip (Neuron Chip), the master-slave processor structure is often used for complex applications, and the master processor completes the user's application functions, the Neuron chip is used as the communication coprocessor. Because it can improve the processing capability of nodes and save money and development time, the versatile General embedded main processor has a good application prospect. The MSP430F149 main processor used in this article is based on TI's high integration chip, which simplifies the hardware design of the application system and is suitable for use as a multi-purpose intelligent node.

2 Introduction and implementation of consumer Stack

2.1 Structure of a stack

Elastic stack microserver is a set of development kits provided by Echelon. Its structure is as follows:

Figure 1 Producer stack structure

The figure shows that the communication between the master processor and the consumer stack microserver is implemented through the consumer stack API function. Five of them are usually used: lonInit (), lonEventHandler (), lonPropagateNv (), lonPollNv () and lonsendServicePin (). The slave stack Micro Server runs the firmware of the slave stack and the LonTalk protocol ~ Layer 6: the master processor runs the SCI serial port driver and the consumer stack API function to process communications with other Lonworks nodes. The master processor application calls the consumer stack API function. The Interface Support file of the main processor device, which is generated by the Neuron C model file using the secure stack wizard. The data table defines Network Variables and transceiver parameters. The Model file only needs to declare the network variable NVs and configure the attribute CPs and the function module FBs. Therefore, you do not need to be familiar with Neuron C.

The serial driver provides an independent interface between the master processor and the slave processor. The entire serial driver consists of two parts: the upper-layer driver provides an interface for the main application; the lower-layer driver completes the hardware interface with the Neuron chip. Data exchange between the upper and lower-layer drivers is completed through the Buffer Queue. Communication between the underlying driver and the slave processor includes two types: SCI upload and SCI download. SCI upload is the data uploaded from the Neuron chip to the master processor; SCI downstream data is transmitted from the master processor to the Neuron chip.

2.2 consumer StackSoftware Implementation

Use the provided Neuron C template for case modification. It mainly modifies the statements related to the MSP430F149 processor in ldvsci. h and ldvsci. c.

In ldvsci. h, modify it:

# Define ENABLE_RX_TX () (ME1 | = UTXE0 + URXE0)

# Define enable_tx_isr () (ie1 | = 0x80)

# Define enable_tx_complete_isr () (ifg1 | = 0x80) // usart0 sending flag

# Define enable_rx_isr () (ie1 | = 0x40) // enable Sci receive interrupt

# Define disable_tx_isr () (ie1 & = ~ 0x80)

# Define disable_tx_complete_isr () (ifg1 & = ~ 0x80) // reset the usart0 sending flag

# Define disable_rx_isr () (ie1 & = ~ 0x40)

# Define CHECK_RTS () (P2OUT & 0x02) // check RTS

# Define CHECK_CTS () (P2IN & 0x01) // check CTS

# Define ASSERT_RTS () (P2OUT & = ~ 0x02) // assert RTS

# Define DEASSERT_RTS () (P2OUT | = 0x01) // deassert RTS

# Define DEASSERT_HRDY () (P2OUT | = 0x04) // deassert _ HRDY

# Define ASSERT_HRDY () (P2OUT & = ~ 0x04) // assert _ HRDY

In ldvsci. h, void SysResetSCI (void), void SysInit (void ),

Void SysUpdateWDT (void), @ interrupt void RxInt (void) and programs related to MSP430F149 in @ interrupt void TxInt (void.

In other files, the difference between platform. h defines BIG_ENDIAN and LITTLE_ENDIAN, which corresponds to the Harvard structure and the Von noriman architecture. Because the MSP430F149 core is built by the Von nuoman architecture, the stacking stack needs LITTLE_ENDIAN (that is, the high byte has a high address ).

2.3Consumer StackHardware Implementation

The slave processor (2) uses a TP/FT-10F control module, which consists of a micro-circuit board, including a 3150 chip, a flash memory, a communication transceiver, power connector, I/O port and network interface, IO_0 ~ IO_10 is the 11 I/O pins of the neuron chip 3150 used to connect the control device. DataA and DataB are the connection interfaces between the FTT-10 transceiver and the network, it can send the data processed and output by the main processor to the LON bus, or send messages on the LON bus to the main processor.

Communication between the main processor and the neuron chip adopts the SCI mode. The SCI interface is a half-duplex Serial Asynchronous communication interface. The communication format is: one start bit, eight data bits, and one stop bits (LSB first ). The choice of communication mode is determined by IO3, and IO3 is grounded by SCI communication mode. IO5 and IO6 are used to select the communication rate.

Transplantation of 3μcos _ Ⅱ

All source code of μCOS _ Ⅱ, a total of 16 files. The source files involved in the porting work are divided into three parts: the code that is irrelevant to the processor, which completes the basic functions of the operating system, including 10 files: OS _CORE.C, OS _MBOX.C, OS _MEM.C, OS _Q.C, OS _SEM. c, OS _TASK.C, OS _TIME.C. OS _FLAG.C, OS MUTEX. c, uCOS_II.H. The setup code section contains the OS-CFG.H and the pair des. H header files for operating system configuration.

Figure 2 master-slave processor connection

The main part is the Code related to the processor, including a header file OS _CPU.H, a C code file OS _CPU_C.C, and an assembly file OS _CPU_A.ASM, Which is transplanted to the MSP430F149 processor, the three architecture-related files need to be modified. The Code volume is about 500 lines. The following describes how to port these three files.

OS _CPU.H contains the data type definition, stack unit definition, stack growth direction definition, the macro definition of Guanzhong disconnection and open interruption, and the macro definition of task switching. To call the underlying interface functions of the system in different working modes, SWI is interrupted. The unit of the stack is the same as the length of the CPU register. The structural constant OS _STK_GROWTH is set to 1, indicating that the stack increases from high address to low address.

OS _CPU_C.C requires six simple c functions: OSTaskSiklnit (); OSTaskCreateHook (); OSTaskDelHook (); OSTaskSwHook (); OSTaskStatHook (); OSTimeTickHook () the only necessary function is OSTaskStklnit (). The other five functions must be declared but not included. For OSTaskStklnit (), OSTaskCreate () and OSTaskCreateExt () call OSTaskStkInit () to initialize the stack structure of the task. OSTaskStkInit () returns the address referred to by the stack pointer () the address is obtained and saved to the task control block (OS TCB.

CPU _ A. ASM requires four simple assembly language functions: OSStartHighRdy (); OSCtxSw ();

OSIntCtxSw (); OSTickISR (). Put all processor-related code in the OS _CPU_C.C file, instead of some scattered assembly language files.

(1) OSStartHighRdy (): To run the high-priority ready task function OSStartHighRdy (), you must call OSTaskSwHook () Because OSTaskSwHook () can be determined by checking OSRunning as OSStartHighRdy () when you call it (OSRunning is FALSE) or a normal task is switched over to call it (OSRunning is TRUE ). OSStartHighRdy () must also set OSRunning to TRUE before the highest priority task is restored and after OSTaskSwHook () is called.

(2) OSCtxSw () and OSIntCtxSw (): Context switching function task-level switching is completed by sending Soft Interrupt commands, where the broken vector address must point to OSCtxSw (). OSIntExit () calls OSintCtxSw () to implement the interruption-level switching function.

(3) OSTickISR (): the scheduled interrupt function OSTickISR () is mainly used to save the Processor register content when the inner interrupts, restore the Processor register content when the task switches out, and return the content, it is equivalent to the entry to interrupt the service program.

Combination of 4μc/OS _ Ⅱ and hybrid Stack

Because of the inherent features of the embedded operating system code of μC/OS _ Ⅱ and the application code of hybrid stack, the two can be organically combined. μCOS _ Ⅱ is defined by system services, such as mailbox, memory management, message queue, and semaphore management. These services are defined in OS _CFG.h, to use these services, you only need to change the defined value to 1. Put all constant definitions in the consumer stack application in OS _CFG.h. In this way, various service functions of the operating system and consumer stack APIs and APP functions can be reduced at the same time.

Run the consumer stack application as a task of the μCOS _ Ⅱ operating system. First, define the stack to save the current value of the MCU register when the task is switched. When μCOS _ Ⅱ is scheduled to run the task next time, the CPU value can be restored from the stack, this task continues to run. The procedure is as follows:

OS _STK TaskStartStk [TASK_STK_SIZE]; // task stack of Task 1

OS _STK worker stackstk [TASK_STK_SIZE]; // The task stack of the worker Stack

... // Other task stacks

Void main (void)

{

OSInit ();

OSTaskCreat (Task1, (void *) 0, & TaskStartStk [TASK_STK_SIZE-1], 0 );

OSTaskCreat (Consumer stack, (void *) 0, & Consumer stackstk [0], 2 );

... // Create other tasks

OSStart ();

Return 0;

}

Void consumer stack (void)

{

LonInit ();

For (;;)

{

LonEventHandler (); // periodic call checks whether any LonWorks event is to be handled

}

}

Because the μC/OS _ Ⅱ operating system does not have any hardware drivers, you can expand the serial port driver and input/output queue operations of the stacking stack as part of the operating system. In addition, the system can add other specific tasks to achieve reasonable utilization of nodes through System Scheduling and increase node practicability. 4.

Finally, the MSP430F149 chip with the TP/FT-10F control module is connected to the Gizmo4 Development Board, compiled by Nodebuilder development tool, enter the debugging interface, connect to the two nodes network using LonMaker, and test whether the two nodes communicate.

Figure 4 software structure

5 conclusion

MSP430F149 is a 16-bit Proteus microprocessor, which is especially suitable for handheld devices and cost-effective, low-power network devices, it integrates various resources such as interrupt control, power control, storage control, UART, PWM, and ADC. Due to the demands of industry and home networking, and the convenient LonWorks bus network access mode, this multi-purpose intelligent node can be scattered and self-developed, and each node can solve its specific tasks in a distributed manner, on the other hand, through point-to-point and point-to-point communication, information transmission between nodes is achieved, and convergence is achieved based on decentralization. To monitor and manage the LON network, the upper computer must be able to exchange dynamic data. LON bus technology also provides DDE Server software. The DDE Server can exchange network variables and information between the LON network and any Windows applications with the DDE function. The system provides users with a friendly man-machine interface. You can use the host computer to set the real-time running status of each node, as well as historical running records and printing.

The author's innovation point: using the hybrid stack technology, a general node with MSP149 as the main processor and Neuron chip as the microprocessor is designed to achieve communication connection with the Lonworks bus, and can be extended for multiple purposes, it has good practical and economic value.