(First input first
Output, first-in-first-out queue) This is a traditional method of execution in order, the first entry command is completed first and then pulled back, followed by the execution of the second command.
1. What is FIFO?
First in first out
The abbreviation is an advanced and FIFO data cache. The difference between it and common storage is that there is no external read/write address line. This is very simple to use, but the disadvantage is that it can only write data in sequence, for sequential data reading, the data address is automatically added by the internal read/write pointer by 1. It cannot be determined by the address line as in general memory to read or write to a specified address.
2. Under what circumstances should I use FIFO?
FIFO is generally used for data transmission between different clock domains, such as AD data collection at one end of FIFO and PCI bus of the computer at the other end. Assume that the ad acquisition rate is 16 bits.
SPS, the data volume per second is 1.6 kb × 16 bit = 1056 Mbps, while the PCI bus speed is 33 MHz, the bus width is 32 bit, and its maximum transmission rate is Mbps, FIFO can be used as a data buffer between two different clock domains. In addition, FIFO can be used for data interfaces of different widths, such as single-chip microcomputer bit 8-bit data output, while DSP may be a 16-bit data input, when the single-chip microcomputer is connected to the DSP, the FIFO can be used for data matching.
3. Some important parameters of FIFO
Width of the FIFO: the width of
Width, which is only the data bit of the first read/write operation of the FIFO, just as the MCU has 8 and 16 bits, arm
32-bit and so on. The width of the FIFO is fixed in a single-chip IC. You can also choose one. If you use FPGA to implement a FIFO, its data bit, that is, the width can be customized.
Depth of FIFO:
Deepth, which refers to the number of N-bit data that can be stored in the FIFO (if the width is N ). For example, an 8-bit FIFO, if the depth is 8, it can store 8 8-bit data with a depth of 12
You can store 12 8-bit data. The depth of the FIFO can be large or small. I personally think that there is no fixed formula for calculating the depth of the FIFO. In actual work, the full/empty mark of the data in the FIFO can control the data to continue writing or reading. In a specific application, it is impossible to calculate the exact required FIFO depth by some parameters, which is feasible when the write speed is better than the read speed, however, in actual use, the FIFO depth is usually greater than the calculated value. Generally, you can estimate the approximate width and depth based on the specific situation of the circuit while taking into account the system performance and FIFO cost. For applications whose write speed is slower than the read speed, the depth of the FIFO should be determined by the specific requirements based on the read data structure and read data.
Full sign: A signal sent by the FIFO status circuit when the FIFO status is full or is about to be full, to prevent the FIFO write operation from continuing to write data to the FIFO status and causing overflow (overflow ).
Empty flag: A signal sent by the FIFO status circuit when the FIFO is empty or is to be empty, in order to prevent the read operation of the first-in-first-out from reading data from the first-in-first-out, leading to the reading of invalid data (underflow ).
Read clock: the clock that the read operation follows. Data is temporarily read along each clock edge.
Write clock: The Clock followed by write operations. Data is temporarily written along each clock edge.
Read pointer: points to the next read address. Automatically add 1 after reading.
Write pointer: point to the next address to be written. After writing, add 1 automatically.
A read/write pointer is actually a read/write address, but this address cannot be selected randomly, but it is continuous.
4. FIFO Classification
The root clock domain that uses FIFO, which can be divided into synchronous FIFO and asynchronous FIFO. Synchronous FIFO refers to the same clock as the read clock and write clock. A read/write operation occurs temporarily along the clock edge. Asynchronous FIFO indicates that the read/write clock is inconsistent and the read/write clock is independent of each other.
5. Difficulties in FIFO Design
The difficulty of the FIFO design lies in how to judge whether the FIFO is empty or full. To ensure that the data is correctly written or read, without the benefit or read null status, you must ensure that the FIFO is full and cannot perform write operations. Read operations cannot be performed in an empty state. How to judge whether a FIFO is full or empty becomes the core issue of the FIFO design. Because synchronous FIFO is rarely used, only the null/full mark of Asynchronous FIFO is described here.
In the design of the trigger, it is inevitable that the sub-steady state problem will occur (for details about the sub-steady state, refer to the relevant information ). In the circuit involving the trigger, the sub-steady state cannot be completely eliminated. You can only find a way to minimize the probability of its occurrence. One of the methods is to use the Gray code. The gray code is transformed by only one digit between two adjacent code elements (in many cases, many code elements change at the same time ). This will avoid the sub-steady state when the counter is synchronized with the clock. However, the gray code has the disadvantage that it can only define 2 ^ n depth, rather than the random definition of the FIFO depth as the binary code, because the Gray code must cycle a 2 ^ N, otherwise, the difference between two adjacent code elements cannot be guaranteed, so it is not a real thunder code. The second is to use a redundant trigger. Assuming that the probability of a trigger's sub-steady state is P, the probability of two and the associated trigger's sub-steady state is the square of P. However, this increases latency. The occurrence of the sub-steady state will cause a FIFO error. The address pointer of the read/write clock sample will be different from the actual value, which leads to an incorrect write or read address. Due to the delay, the null/full mark is not necessarily generated when the FIFO is really empty/full. The "null"/"full" sign may appear when the FIFO is not empty or full. This is nothing bad, as long as the FIFO does not appear Overflow
Or underflow is OK.
Many articles about FIFO actually discuss different algorithms with null or full signs.
In the asynchronous FIFO structure document of nebhrajani, the author proposes two algorithms for the FIFO null/full mark.
First Algorithm: Construct a FIFO with a pointer width of N + 1 and a depth of 2 ^ n Bytes (convert the gray pointer to a binary pointer for the comparison of the cursor ). When the highest bits in the binary code of the pointer are inconsistent and the other N bits are equal, the FIFO is full (in Clifford
In Cummings's article, the gray Code indicates that the first two are not the same, and the last two LSB are the same as full, which is the same as the binary representation of MSB ). When the pointer is completely equal, the FIFO is null. This may not be easy to see. An example shows how a 8-byte FIFO works (using a pointer that has been converted to binary ). Required o_width = 8, required o_depth =
2 ^ n = 8, n =
3. the pointer width is n + 1 = 4. At first, rd_ptr_bin and wr_ptr_bin are both "0000 ". In this case, 8 bytes of data are written into the FIFO. Wr_ptr_bin
= "1000", rd_ptr_bin = "0000 ". Of course, this is the full condition. Now, assume that eight read operations are performed to make rd_ptr_bin
= "1000". This is an empty condition. The other 8 write operations will make wr_ptr_bin
Equal to "0000", but rd_ptr_bin is still equal to "1000", so FIFO is a full condition.
Obviously, the starting pointer does not need to be "0000 ". Suppose it is "0100" and the FIFO is empty, then 8 bytes will make wr_ptr_bin
= "1100", rd_ptr_bin is still "0100 ". This also indicates that the FIFO is full.
This article about Asynchronous FIFO structure by nebhrajani describes how to use the Gray code to set the condition of full space, however, it is not clear why the read/write pointer of a FIFO with a depth of 8 must be implemented with a 3 + 1 gray code, while a 3 + 1 gray code can represent a 16-bit depth, the real FIFO is only 8 bits. What is the problem? This problem lies in Clifford.
Cummings is explained in the article. A three-digit Gray Code represents the depth of eight digits. If one digit is the most MSB, the gray code composed of the other three digits does not represent the new address, that is to say, the gray code 0100 represents 7, while the 1100 represents 7, but the Gray Code enters a cycle with 1 as MSB after a loop with 0 bits in MSB, then we enter a zero-bit MSB loop, and the other three-digit code is still gray code, but this creates a problem. After the 0100 loop is complete, we enter 1000, two of them undergo a transformation instead of one bit. Therefore, the addition of An MSB makes the code in two places: 0100 ~ ~ 0000 two code elements have changed, so this code is not a real Gray code. The added MSB is used to calculate the null full mark. Vijay
In the nebhrajani article, the gray code is used to convert the Gray code to the binary code. When the Gray code is converted, the null full condition is proposed. Only two conversions are performed, while the Clifford
In Cummings's article, the condition of null full is obtained directly under the condition of Gray code. In fact, the two are the same, but their implementation methods are different.
The second algorithm: style mentioned in Clifford E. Cummings
#2. It divides the FIFO address into four parts, each of which uses the MSB 00, 01, 11,
10 determine whether the FIFO is going full or going empty
(To be full or empty ). If the number of two MSBs whose write pointer is higher than the value of two MSBs whose read pointer is higher than the value of two MSBs, the FIFO value is "almost full ",
If the number of two MSBs with a write pointer is greater than the value of two MSBs with a read pointer, the FIFO is "almost empty ".
The third part of nebhrajani's asynchronous FIFO structure also mentions a method, that is, the direction signs and thresholds. Set 75% of the FIFO capacity as the upper limit and 25% of the FIFO capacity as the lower limit. When the direction sign exceeds the threshold, the full/empty sign is output.
E. The style mentioned in Cummings
#2 is similar. They all belong to the conservative empty-filled judgment. In fact, the output is empty and full. The FIFO is not necessarily empty/full.
Speaking of this, we have clearly seen that the most important part of the FIFO design is that different algorithms that generate null/full signs generate different FIFO. However, whether it is accurate, empty, full, or conservative, it is to ensure the reliability of the FIFO operation.
GPIF (General programmable
Interface), that is, universal programmable interface, is the Cypress company in its EZ-USB
A user-programming interface designed in FX and fx2 series single-chip microcomputer is fast and flexible. It can be seamlessly connected to peripheral devices using multiple protocols, such As Eide/atapi, ieee1284, and utopia. You can program it as needed without CPU intervention during running. It only uses some CPU signs and interrupts communication with the enhanced 8051 kernel.
In the GPIF mode, the internal is a master, and the peripheral to be controlled is a slave,
Both the Read and Write signals and some control signals are sent by fx2. The peripheral only provides you with a write handshake signal connected to your rdyx signal, which is used to control the waveform;
In the FIFO mode, your peripheral is used as the master, and fx2 is used as the slave. The read and write signals are provided externally! Fx2 does some configuration work!
As for the Advantages and Disadvantages: for GPIF, the firmware is a little more complicated! Of course, it is not difficult if you have learned it! When I started to use it, I thought it was a bit complicated because it involved the problem of GPIF waveform. If I designed this waveform well, I had to pay attention to it! Of course, you can download a document on the Internet to explain the GPIF Waveform Design!
In addition, the theoretical speed of GPIF is higher than that of Slave FIFO!
If you are writing firmware, it is relatively simple! Well ......, Do more work on the periphery! In addition, his theoretical speed is not as high as that of GPIF!