DMA Learning Based on stm32f103zet6

Source: Internet
Author: User

Introduction to internal integrated ADC of stm32
I. The reference voltage range is
/* 2.4V ≦ V
Listen 3.6 V
Therefore, its input analog voltage range is 0 <= V */
2. When a negative voltage is measured or the measured voltage signal is out of the range, it must first be translated through the calculation circuit or by using the resistance partial pressure.
3. I use the 10 k resistance of 51 Single-Chip Microcomputer to simulate input.
Iv. Rule channel and injection Channel
/* The so-called rule is played by common sense. We can call it a normal channel. What corresponds to it is the injection channel, which is
When the rule Channel is being converted, it can be interrupted by the injection channel, instead of executing the injection channel conversion.
After the conversion, the conversion in the rule Channel will continue. The rule Channel group of TM32ADC can contain up to 16 conversions, while the injection Channel
The Group can contain up to four channels */
5. This is required to initialize the ADC. biandong has a struct to initialize the ADC.
1. First, determine where to input our analog quantity?
This involves the knowledge of the ADC channel. Each ADC channel corresponds to a GPIO pin port.
The default reuse function of PC0 is ADC1, ADC2, and ADC3 Channel 10.
So we should first configure GPIO. Now we can make a guess.
2. Configure GPIO

GPIO_Mode = GPIO_Mode_AIN
GPIO_Pin = GPIO_Pin_10
GPIO_Speed = GPIO_Speed_50MHz
The above is the simulated input.
6. Configure the ADC, that is, initialize the ADC,
Find such a struct
Adc_inittypedef
Struct members include {
Functionalstate adc_continuousconvmode
Uint32_t adc_dataalign
Uint32_t adc_externaltrigconv
Uint32_t adc_mode
Uint8_t adc_nbrofchannel
Functionalstate adc_scanconvmode
}
1. The value of adc_continuousconvmode is
Specifies whether the conversion is already med in continuous or single mode.
This parameter can be set to enable or disable
This parameter is used to configure whether to enable loop collection enable or disable
2. adc_dataalign indicates data alignment. Its values include:
# Define adc_dataalign_left (uint32_t) 0x00000800)
# Define adc_dataalign_right (uint32_t) 0x00000000)
# Define is_adc_data_align (align)
Align left and right ..
3. How does ADC_ExternalTrigConv trigger external interruptions? Its values include:
# Define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO (uint32_t) 0x000C0000)
# Define ADC_ExternalTrigConv_None (uint32_t) 0x000E0000)
# Define adc_externaltrigconv_t1_pc3 (uint32_t) 0x00000000)
# Define ADC_ExternalTrigConv_T1_CC2 (uint32_t) 0x00020000)
# Define ADC_ExternalTrigConv_T1_CC3 (uint32_t) 0x00040000)
# Define ADC_ExternalTrigConv_T2_CC2 (uint32_t) 0x00060000)
# Define ADC_ExternalTrigConv_T2_CC3 (uint32_t) 0x00020000)
# Define adc_externaltrigconv_t3_pc3 (uint32_t) 0x00000000)
# Define ADC_ExternalTrigConv_T3_TRGO (uint32_t) 0x00080000)
# Define ADC_ExternalTrigConv_T4_CC4 (uint32_t) 0x000A0000)
# Define adc_externaltrigconv_t5_pc3 (uint32_t) 0x000A0000)
# Define ADC_ExternalTrigConv_T5_CC3 (uint32_t) 0x000C0000)
# Define ADC_ExternalTrigConv_T8_CC1 (uint32_t) 0x00060000)
# Define ADC_ExternalTrigConv_T8_TRGO (uint32_t) 0x00080000)
There are many triggering methods, of course, ADC_ExternalTrigConv_None, which means that the external interrupt mode is not used for triggering (so the software triggers)
4. What is the ADC_Mode ADC mode?
Configures the ADC to operate in independent or dual mode.
This parameter can be a value of ADC_mode
Its values include:
# Define ADC_Mode_AlterTrig (uint32_t) 0x00090000)
# Define ADC_Mode_FastInterl (uint32_t) 0x00070000)
# Define ADC_Mode_Independent (uint32_t) 0x00000000)
# Define ADC_Mode_InjecSimult (uint32_t) 0x00050000)
# Define ADC_Mode_InjecSimult_FastInterl (uint32_t) 0x00030000)
# Define ADC_Mode_InjecSimult_SlowInterl (uint32_t) 0x00040000)
# Define ADC_Mode_RegInjecSimult (uint32_t) 0x00010000)
# Define ADC_Mode_RegSimult (uint32_t) 0x00060000)
# Define ADC_Mode_RegSimult_AlterTrig (uint32_t) 0x00020000)
# Define ADC_Mode_SlowInterl (uint32_t) 0x00080000)
It seems that there are injection groups and rule groups. Some words are not very familiar. It doesn't matter. Let's do it first! Use again
5. ADC_NbrOfChannel sampling channel?
Obviously, 16 rule channels are generally used, and the value is 1-16
Specifies the number of ADC channels that will be converted using the sequencer for regular
Channel group. This parameter must range from 1 to 16
6. ADC_ScanConvMode. read the manual.
Specifies whether the conversion is saved med in scan (multichannels) or single (one channel)
Mode. This parameter can be set to enable or disable
Scan is used when multiple channels exist. If only one channel is used, a single channel is selected.
The value is enable or disable.
Now that the structure member analysis is complete, Let's guess how to assign values and declare: single channel acquisition, right alignment (convenient data storage)
Software-triggered, with 10 channels (using pc0)
Adc_initstructure.adc_continuousconvmode = Enable
Adc_initstructure.adc_dataalign = adc_dataalign_right
Adc_initstructure.adc_externaltrigconv = adc_externaltrigconv_none
Adc_initstructure.adc_mode = adc_mode_independent
Adc_initstructure.adc_nbrofchannel = 11
Adc_initstructure.adc_scanconvmode = Disable
Let's take a look at the original code:
/* Adc1 configuration */
Adc_initstructure.adc_mode = adc_mode_independent;
Adc_initstructure.adc_scanconvmode = Enable;
Adc_initstructure.adc_continuousconvmode = Enable;
Adc_initstructure.adc_externaltrigconv = adc_externaltrigconv_none;
Adc_initstructure.adc_dataalign = adc_dataalign_right;
Adc_initstructure.adc_nbrofchannel = 1;
Adc_init (adc1, & adc_initstructure );
Obviously there are still many errors. It doesn't matter. analyze them slowly
1. Because it is a channel that does not need to be scanned, 2nd errors are reported.
2. The number of channels is incorrect. I thought it was the specified channel. It turns out to be number of channel.
3. The good thing is that the call of a library function is missing. This is indeed a lack of awareness!
7. Since DMA is used to transmit data, initialize DMA next! The DMA knowledge is not analyzed for the time being.
Let me take a look at the concept of DMA!
1. stm32 is perfect. Each module can have a struct to organize some of its parameter configurations. I even think it is as flattering as uboot.
This is just my ignorance. It is also such a struct dma_inittypedef dma_initstructure;
Follow the manual
2. dma_inittypedef {
Uint32_t dma_buffersize
Uint32_t DMA_DIR
Uint32_t DMA_M2M
Uint32_t DMA_MemoryBaseAddr
Uint32_t DMA_MemoryDataSize
Uint32_t DMA_MemoryInc
Uint32_t DMA_Mode
Uint32_t DMA_PeripheralBaseAddr
Uint32_t DMA_PeripheralDataSize
Uint32_t DMA_PeripheralInc
Uint32_t DMA_Priority
}
3. DMA_BufferSize, which is obviously the data size. See how she describes it.
Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal
The configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in
The transfer direction
We can conclude that DMA_PeripheralDataSize = DMA_MemoryDataSize = DMA_BufferSize
The value can be
# Define dma_memorydatasize_byte (uint32_t) 0x00000000)
# Define dma_memorydatasize_halfword (uint32_t) 0x00000400)
# Define dma_memorydatasize_word (uint32_t) 0x00000800)
4. Why is the dma_dir literal not clear? View explanations
Specifies if the peripheral is the source or destination. This parameter can be a value
Dma_data_transfer_direction
Data Source and target source
Value
# Define dma_dir_peripheraldst (uint32_t) 0x00000010)
# Define dma_dir_peripheralsrc (uint32_t) 0x00000000
From memory to peripherals or from peripherals to memory
5. dma_m2m I can guess that the role of DMA is as follows: m to m is not mentioned above.
# Define dma_m2m_disable (uint32_t) 0x00000000)
# Define dma_m2m_enable (uint32_t) 0x00004000)
You can set it like this.
6. dma_memorybaseaddr and dma_peripheralbaseaddr
The two can be viewed together. The literal meaning is clear. The peripheral address and the memory (variable) Address depend on your address.
7. dma_memoryinc and dma_peripheralinc are not familiar with variable names. Is the interrupt triggered? View explanations
Specifies whether the memory address register is incremented (adj. Added) or not.
This parameter can be a value of dma_memory_incremented_mode
Add address? To understand a serious error, it means that the address increments, that is, multiple channels can be collected continuously? Continue analysis
8. dma_mode: DMA mode. What mode does it have? View explanations
Specifies the operation mode of the dmay channelx.
This parameter can be a value of dma_circular_normal_mode
The circular buffer mode cannot be used if the memory-to-memory
Data transfer is configured on the selected channel
Optional values:
# Define dma_mode_circular (uint32_t) 0x00000020)
# Define dma_mode_normal (uint32_t) 0x00000000)
Is the normal and cyclic mode a round-sampling? Continue first
9. DMA_Priority priority is easy to understand. Do you want to control the priority? See the explanation and values.
Specifies the software priority for the DMAy Channelx. This parameter can be
A value of DMA_priority_level
Value
# Define DMA_Priority_High (uint32_t) 0x00002000)
# Define DMA_Priority_Low (uint32_t) 0x00000000)
# Define DMA_Priority_Medium (uint32_t) 0x00001000)
# Define DMA_Priority_VeryHigh (uint32_t) 0x00003000
Clearly four priorities
Now, the analysis is complete, and you can guess it.
1. DMA_InitStructure.DMA_BufferSize = 1
2. DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST
3. DMA_InitStructure.DMA_M2M = DMA_M2M_Disable
4. DMA_InitStructure.DMA_MemoryBaseAddr = the single-byte variable of an address unit enables the char-type
5. dma_initstructure.dma_memorydatasize = dma_memorydatasize_byte
6. dma_initstructure.dma_memoryinc = dma_memoryinc_disable no address increment is required.
7. dma_initstructure.dma_mode = dma_mode_circular
8. dma_initstructure.dma_peripheralbaseaddr = serial port address?
9. dma_initstructure.dma_peripheraldatasize = dma_memorydatasize_byte
10. dma_initstructure.ma_peripheralinc = dma_peripheralinc_disable
11. dma_initstructure.dma_priority = dma_priority_veryhigh to the highest
View Source Code
Dma_initstructure.dma_peripheralbaseaddr = adc1_dr_address;
Dma_initstructure.dma_memorybaseaddr = (u32) & adc_convertedvalue;
Dma_initstructure.dma_dir = dma_dir_peripheralsrc;
Dma_initstructure.dma_buffersize = 1;
Dma_initstructure.dma_peripheralinc = dma_peripheralinc_disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init (DMA1_Channel1, & DMA_InitStructure );
It seems a little bad.
1. MA_InitStructure.DMA_DIR is obviously used as a data source.
2. What are the differences between DMA_MemoryDataSize_Byte and DMA_PeripheralDataSize_HalfWord?
I cannot find it in Baidu. First, wait until the experiment is completed and then verify it.
8. There is still much work to do after the struct member Initialization is complete.
1./* ADC1 regular channel11 configuration */
ADC_RegularChannelConfig (ADC1, ADC_Channel_11, 1, ADC_SampleTime_55Cycles5 );
Configure rule Channel 11
2./* enable DMA channel1 */
Dma_cmd (dma1_channe10, enable );
Enable DMA Channel
3./* enable adc1 DMA */
Adc_dmacmd (adc1, enable );
Enable the DMA controller of adc1
4./* enable adc1 */
Adc_cmd (adc1, enable );
Enable adc1
5./* enable adc1 reset calibaration register */
Adc_resetcalibration (adc1 );
/* Check the end of adc1 reset calibration register */
While (adc_getresetcalibrationstatus (adc1); // reset Calibration

/* Start adc1 calibaration */
Adc_startcalibration (adc1 );
/* Check the end of adc1 calibration */
While (adc_getcalibrationstatus (adc1); // Calibration

/* Start adc1 software conversion */
Adc_softwarestartconvcmd (adc1, enable); // triggered by software. Conversion starts at this time.
The result is correct after the hardware test!

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