Follow on Modelsim LPM (FIFO, PLL) Simulation

When using third-party software: Modelsim to simulate Quartus ii lpm, you must add the. V file generated by examples and add the. V file to the Altera library during simulation, as shown below:

(By the way, only one testbench top-level file in Modelsim can exist .... None of the books ..)

 

LPM-PLL note:

Today, when Modelsim is used for a post-simulation, it is found that there is no output of the PLL. When setting different test clock frequencies, there are three situations:

(1) When the input clock cycle is less than the input clock cycle selected in the sample PLL, the following warning message is displayed during simulation:

Warning: Input clock freq. Is under VCO range. Cyclone iii pll may lose lock

(2) When the input clock cycle is greater than the input clock cycle selected in the sample PLL, the following warning message is displayed during simulation:

Warning: Input clock freq. Is Over VCO range. Cyclone iii pll may lose lock

In the above two cases, the PLL will not work normally. In the first case above, you can set a larger period for the input test clock. In the second case, you can set a lower cycle for the input test clock.

(3) When the input clock cycle is equal to the input clock cycle selected in the sample PLL, the following information appears during simulation:

Note: Cyclone iii pll locked to incoming clock

In this case, the PLL can work normally! Note:

Waveform simulation is as follows:

 

By the way, the art of Modelsim is: