Design of FIR Filter Extraction Based on FPGA

Abstract: This paper introduces the working principle of the FIR extraction filter, focuses on the method of using xc2v1000 to implement the FIR extraction filter, and gives the simulation waveform and design features.
Key words: FIR Filter extraction; pipeline operation; FPGA

It is complicated to use FPGA to implement the extraction filter, mainly because FPGA lacks an effective structure to implement multiplication. Now, FPGA integrates hardware multiplier, FPGA has made great progress in digital signal processing. This paper introduces a design method of FIR Filter Based on xc2v1000 of Xilinx.

Implementation
Structure Design
Based on the working principle of the extraction filter, xc2v1000 is used in this paper to implement a 3-step FIR extraction filter with a extraction rate of 2 and a linear phase. The source file is designed using schematic diagram and VHDL. Figure 1 shows the top-layer schematic of the filter extraction. Here, clock is the working clock, reset is the reset signal, enable is the effective signal of input data, data_in () is the input data, data_out () is the output data, valid is the valid signal of output data. Adder18 is a multiplier module, mult18 is a multiplier module, acc36 is a accumulator module, signal_36to18 is a data bitrate device module, and fir_controller is a controller module. The Controller periodically sends data or control signals to the processors, multiplier, and accumulators to implement pipeline operations.

Figure 1 principle of Top-layer filter Extraction

Controller

The Controller is the core module of the filter extraction. It has two functions: receiving input data and sending data and control signals to other modules. Based on the timing characteristics of the processors, multiplier, and accumulators, it regularly sends the data to the multiplier, sends the coefficient to the multiplier, and sends the control signal to the accumulators, let the processors, multiplier, and accumulators complete the specified tasks in each clock cycle to implement pipeline operations. The Controller is described in VHDL and registers are used to store the headers and coefficients. Adder

The input and output of the adder are both 18 BITs, which are described in VHDL. It has two working clock latencies. When the input data is ready, the first clock gets the addition result, and the second clock locks the addition result to the output.

Multiplier

The multiplier is 18-bit input and 36-bit output. It is implemented using the library components mult18x18s and 36-bit latches. Mult18x18s is an 18 × 18bit hardware multiplier that comes with xc2v1000. A single clock can complete the multiplication operation. The 36-bit latches work on the rising edge of the clock, which is described in VHDL. The multiplier (mult18) also has two clock latencies. When the input data is ready, the first clock gets the result of multiplication, and the second clock locks the output of the result of multiplication. The divider and multiplier adopt the lock output structure. Although a working clock delay is added, it is conducive to the stable operation of the extraction filter and the reliability is improved.

Accumulators

The 36-bit accumulators are used to accumulate the output of the multiplier and obtain the filtering result. It has a control port CLR. When CLR is high, the previous round of accumulation results are output and initialized, and a new round of accumulation starts. When CLR is low, the accumulation operation is performed. The accumulators are described in VHDL.

Data Truncation

The data tolerance is described in VHDL, which is used to handle the 36bit output of the accumulators. Generally, the low part of the data is truncated and the data is retained. In order to simulate the function of the extraction filter, we cut off the 18-bit high data and keep the 18-bit low data.

Working Process and function simulation

The following describes how to use an extraction filter to complete a filtering process.

Assuming that the clock 1, clock 2, clock 3, and clock 4 controllers have received data X (n-3), x (n-2), x (n-1), and x (n), then:

Clock 5: The controller sends data x (n) and X (n-3) to the calculator );

Clock 6: The Sub-device for x (n) + x (n-3) operations; the Controller to the sub-device to send data X (n-1) and X (n-2 );

Clock 7: The addition of X (n-1) + x (n-2) operations, output x (n) + x (n-3) operation results. The sending coefficient h (0) from the Controller to the multiplier );

Clock 8: The Multiplier outputs x (n-1) + x (n-2) operation results, multiplier H (0) [x (n) + x (n-3)] operation, the sending coefficient H (1) from the Controller to the multiplier );

Clock 9: multiplier H (1) [x (n-1) + x (n-2)] operation, output H (0) [x (n) + x (n-3)] operation result. The controller sends control signals to the accumulators (CLR is high );

Clock 10: multiplier outputs H (1) [x (n-1) + x (n-2)] operation results. Initialize the accumulators and start the accumulate operation. The controller sends control signals to the accumulators (CLR is low );

Clock 11: accumulators accumulate: H (0) [x (n) + x (n-3)] + H (1) [x (n-1) + x (n-2)]. The controller sends control signals to the accumulators (CLR is high), and the Controller outputs valid signals for filtering data (valid is high );

Clock 12: accumulators output H (0) [x (n) + x (n-3)] + H (1) [x (n-1) + x (n-2)] accumulate results, initialize and start a new round of accumulate operations. Invalid signal output from the Controller (valid is low ).

The above is the whole process of filtering a filter extraction. It can be seen that 8 working clocks are required for output from x (n) input to Y (n) filtering result. If the Controller continuously sends a pumping, coefficient, and control signal to the multiplier and the multiplier, it will form a pipeline operation. Every two clocks, the extraction filter will output a filtering result.

Two considerations

(1) the sum of two n-bit binary numbers requires at least N + 1 binary numbers to be correctly expressed. In this design, the input/output of the divider are all 18bit. To prevent the divider from overflow, ensure that the maximum two digits of the 18bit input data x (n) are the same (both are symbol bits ).

(2) In order to achieve the multi-level series structure of the extraction filter, unified input data effective signal enable and output data effective signal valid timing requirements should be made. This design specifies that the controller sends valid signals from the filtering result at the next clock after the filter result is output by the accumulators, and the time width is a working clock cycle.

Design Features　

Using this design structure to implement the extraction filter has the following three features:

(1) saves on-chip resources and improves resource usage efficiency. Because the filters generated by using the IP Core often cannot reasonably use the resources in the chip based on the actual situation, resulting in a waste of resources. This design uses the pipeline structure, all functional modules are working at full capacity, no idle wait clock, thus saving on-chip resources and improving resource utilization.

(2) multi-level structure of the extraction filter can be implemented. For the output characteristics of the extraction filter, the same design method can be used to design a level-1 extraction filter, and the data of the first-level output can be extracted and filtered again to realize the structure of the multi-level extraction filter.

(3) flexible design and high scalability. Using registers to store the taps and coefficients is suitable for scenarios where the number of filters is small. If you need to use hundreds of filters, it is best to use the xc2v1000 block ram to store the taps and coefficients, in this case, you only need to slightly modify the logic design of the controller. On this basis, you can also implement a programmable extraction filter.

Conclusion

In this paper, a design method of FIR Filter Using xc2v1000 of Xilinx Company is introduced, which is based on the three-step FIR filter with a linear phase and a extraction rate of 2. The extraction filter designed by this method is flexible and has high resource utilization. It can be widely used in the digital receiving field.

Design of FIR Filter Extraction Based on FPGA