DRAM Memory Introduction (i)

Reprinted from the blog Big god Mike old Wolf Blog:
Http://www.cnblogs.com/mikewolf2002/archive/2012/11/13/2768804.html

Reference: Http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask

SDRAM (Synchronous dynamic random access memory), which synchronously dynamically accesses RAM, typically includes the SDR (single Data rate) SDRAMs and the DDR (Double data rate) Sdra Ms. Gddr SDRAMs and HBM are commonly used in video cards.

As shown, the left side is a common memory strip in the PC system, which is a dual channel 2G memory (dual inline memory Module), usually referred to as a DIMM. We can see the memory chips on the black 128MB memory chip, these memory chips are referred to as IC. The memory is double-sided memory, which means that there are 8 ICS on both sides, a total of 16 ic,16*128m=2gb. The single-sided DIMM is called rank, such as the 2GB memory bar, which is made up of Rank1,rank2 two single-sided, with 8 ICS per face.

Figure I, the composition of DRAM

Each IC typically consists of 8 banks (DDR3 typically 8 BANK,GDDR5 typically have 16banks), which share a memory I/O controller, but can be read and write in parallel within each bank.

Each bank includes a line address decoder, a column address decoder, a sensing amplifier, and a dram memory array. As shown in 2, these memory arrays consist of rows and columns, each row-and-column unit, representing n-bit, usually 8bit or 16-bit " each bit consists of a transistor and a capacitor, in GDDR5 and HBM memory, typically 32Byte", Represents a byte or a word. Each row in the bank consists of one page, and each row includes many columns (the column here refers to a single intersection unit). The smallest unit of memory read and write is these crossover units, which are usually only able to be read and written when they are placed in the sensing amplifier, so it is often time to move data between the line and the sensing amplifier.

Placing a line in the sensing amplifier is called "activate" because this operation activates the bank. The contents of the sensing amplifier are put into line, called "Precharge". Sometimes read or write implies a precharge operation, called Ap-read, or Ap-write,ap (auto Precharge).

Figure Two Bank internal structure

In Figure one each bank consists of a 16k page, each page includes 1k columns, each column is 8bit byte, so a total of 16,384 Rows/bank x 1,024 columns Addresses/row x 1 byte/column Address x 8 stacked banks=128m

For DDR3, we usually say that it is 8n-prefetch (here n is the number of banks per rank), because DDR3, each IC has 8 banks, each bank reads the smallest unit of data is 8bit, a byte. Every time the data reads the request, the 8*8bit=64bitdata is read, regardless of whether the data is all we need, for example, we only need one of these bytes, but reading request reads 8 bytes.

As shown in figure three, SDRAM read and write can usually be described by a simple state machine, its state includes idle, active, precharging one or more bank. As with any other state machine, the transition from one state to another state, and start the data operation in the new state, require some minimum waiting time, which affects the performance of SDRAM read and write data, thus affecting the performance of the whole computer system.

The row and column of memory cells in the Sdarm Bank are crossed ( often called cell ) points, which are used to store data, which is usually made up of capacitors and amplifiers, whose power is attenuated over time due to capacitance characteristics, such as temperature, which can affect its attenuation speed. Therefore, periodic power-up refresh operations are required to maintain the data. The refresh frequency is often dependent on the process of memory die and the design of the cell itself. The memory cell read-write and memory flush have the same effect, but not all memory cells have read and write operations until the capacitance is attenuated until it must be refreshed, so timed refreshes are still required. Usually the refresh operation is done by line or page, and after the refresh, the cell's capacitance is charged. The usual refresh operation period is hundreds of clocks to thousands of clocks.

Before refreshing the command, each bank must first precharged and then be idle, which consumes an TRP delay (the minimum number ofclock cycles required between the Issuing of the Precharge command and activating a different row within the same bank). After a refresh command is complete, all banks are in the Precharge (idle) state, and the number of cycles between the Refresh command and the next activate command (ACT) must be greater than or equal to TRFC (the Row refresh Cycle time).

Figure III, SDRAM data transfer state machine

Due to the data transmission time, there is a certain delay, so there are some of the following symbols describe the data transmission in the bank at each stage of the delay.

Parameters	Symbol	Comments
Row Active Time	TRAS	The minimum number of clock cycles required between a bank active command and issuing the Precharge command.
Row address to Column address Delay	Trcd	The minimum number of the clock cycles required between the activation of a row and accessing columns it.
CAS Latency	Cl	The time between sending a column address to the memory and the beginning of the data in response. This was the time it takes to read the first bit of memory from a DRAM with the correct row already open.
Row precharge Time	TRP	The minimum number of clock cycles required between the issuing of the Precharge command and activating a different row wi Thin the same bank.
Activate to Activate in same bank.	TRC	The minimum number of clock cycles required between the activation of a row activting another row in the same bank.
Burst		The number of data beats in a column access. This is the usually 8 for recent DDR3/GDDR5 devices.

SDRAM in response to read and write commands, the bank must be active, the memory controller by sending the Activate command, specify the accessed Rank,bank and page (row). The time to activate a bank is called Trcd,the Row-column (or Command) Delay, which represents the number of cycles that activate the Send active command, program control logic, and read the memory row and column units to the sense amplifier to read and write.

After bank activation, the sensor amplifier has a full page content, this time, you can launch a read-write command, specify to start reading and writing data from a column. The time it takes to read a byte data from an active page (in a sense amplifier) is called, the Column Address Strobe (CAS) Latency, usually intermittent cl or TCAS, which consists of sending read and write commands on the read-write interface, Program control logic that transmits the contents of the sensing amplifier into the input and output buffers and puts the first word of the data on the memory bus for a total time spent.

A bank can only open a page at a time (this opens refers to the page content into the sensor amplifier), for the open page, we can read and write operations, if you do not need to read and write to the page, you can close the page, The page content is written to the page of the bank's Row and column unit to read and write to the other page. This shutdown is accomplished by launching a precharge command, which can either close a bank or close all open banks in rank.

The Precharge command can be bound to a read-write operation in the bank for a combined operation, sending a read with Auto-precharge (RDA) or write with Auto-precharge (WRA) Instead of a separate read-write Operation command. This will allow the SDRAM control logic to automatically open or close the bank as long as certain conditions are met. Conditions to be met include: (1) a minimum of RAS Activation time (TRAS) have elapsed since the ACT command was issued, and (2) a minimum of R EAD to Precharge Delay (TRTP) had elapse since the most recent READ command was issued.

The Precharge command writes the data in the sensing amplifier to the corresponding page in the bank, and then the DRAM core prepares for the next data access. Precharge the time consumed by an open bank is called the Row Access Strobe (RAS) Precharge Delay, by writing TRP. The time consumed between the two activate commands of the same bank is called TRC, which equals TRAS+TRP. The act command interval for different banks is called the Read-to-read Delay (TRRD).

The following timing icons show the time delay for each phase:

DRAM Memory Introduction (i)