1. Introduction
In recent years, with the rapid development of communication technology, network technology and semiconductor technology, the design of intelligent instrumentation System has entered a new era. Among them, the realization of Internet access is the current development of intelligent instrumentation System hot field and important direction.
The ISP (in System programmability) is of great significance for the realization of the Internet access of intelligent instrument system based on TCP/IP protocol in Systems programmable technology. The so-called "in system programmable" refers to the device, circuit and even the entire system for on-site upgrades and function reconfiguration capabilities. This refactoring can be done during experimental development, during the manufacturing process, or even on the site or over the Internet after the delivery of the user.
Using ISP technology, the hardware system of instrumentation can no longer be a pure fixed structure, but it has flexible structure of some software features, and can even reconfigure functions as needed in the running state. Due to the complexity of the simulation integrated chip manufacturing process, the current ISP technology is mainly used in the digital system design, such as the United States Xilinx Company in FPGA/CPLD and other support ISP technology. At the end of 1999, American lattice company took the lead in making breakthroughs in manufacturing technology, introduced ISPPAC (in System programmable analog Ics), introduced ISP technology into the simulation system, and brought revolutionary changes to the design of intelligent instrumentation system.
Combined with ISP technology, the intelligent instrument system is connected to the Internet through Internet, so it can conveniently realize the remote monitoring, control, maintenance, upgrade and industrial automation of the instrument and meter.
2. Design idea based on ISP technology in instrument and meter system
By making full use of the most advanced ISP technology, the intelligent instrument system designed by us not only has the ability of system-level field programmable, but also can realize remote dynamic reconfiguration of system functions based on TCP/IP protocol, on-site upgrade and communication exchange through Internet.
Generally speaking, the intelligent instrumentation system is divided into 3 modules: CPU, analog system and digital logic system. Here we combine with the latest Ana1og device company with the simulation function of the aduc812mcu,philips pioneered in the industry to support the Internet access of the 16-bit MCU, Lattice Company's latest ispPAC and Xilinx Company's FPGA/CPLD to specifically discuss the implementation of ISP and Internet access to the intelligent instrumentation system design.
3. CPU and ISP technology of instrument and instrument system
CPU is the soul of intelligent instrument and instrument system. The overall performance of the intelligent instrument system depends largely on the advanced nature and flexibility of the CPU.
With the development of semiconductor technology, there have been a lot of enhanced CPU, because the CPU ISP technology for the realization of system networking and remote monitoring of the decisive significance, at the same time, due to the 8-bit MCU in the current intelligent instrumentation System application of the broad, we mainly support ISP technology analog Device company's 8-bit MCU (ADuC812) to discuss the application of ISP technology.
Structure and performance of 3.1aduc812
The ADuC812 of the analog device company consists of 8051 compatible cores, memory, in-chip foreign devices, power units, and analog units. The 8051-compliant kernel rated operating frequency is 12MHz (Max 16MHz), 3 16-bit Timer/counter, features include watchdog timer WDT, Power Monitor PSM, and high-speed ADC to RAM capture DMA controller. There are 8 K-word Flash/electro Erase program memory in the slice, 640-word flash/electric erase data memory and 256-byte-slice data ram, support 16M-byte external data addressing space and 64K-byte external program addressing space, providing 32 programmable UO for multiprocessor interfaces and I/O extensions, Port 3 has a high current drive capability with a standard UART serial port and configurable I2C or SPI interface.
The simulation unit includes 8-channel, High-speed (200KSPS) Self-calibration 12-bit ADC, in-chip 4oppm/. C Voltage Reference, two 12-bit voltage output DAC and in-chip temperature sensor. It can flexibly build a powerful 12-bit data acquisition system.
Both the MCU kernel and the analog converter have normal, idle and power off mode, which provides a flexible management scheme suitable for low consumption.
3.2ADUC812 's ISP in system programming
ADuC812 through the standard UART serial interface implementation and the sequence code download (in the system programming), the user in the ADuC812 serial downloading mode may download the program code through the PC serial port to the chip program memory.
After ADuC812, analog device company also launched the ISP technology to support the 16-bit and 24-bit precision analog MCU ADuC816 and ADuC824 and other products.
4, the design of simulation system and ISP technology
Before the lattice company first introduced high-performance system programmable analog circuit ispPAC in late 1999, the simulation system design often needs to use a large number of standard separation devices to build. With the advent of ispPAC, the precise simulation design of high integration can now be realized by a small monolithic ISPPAC chip, which simplifies and accelerates the design, integration and configuration of analog circuits fundamentally, avoids the disadvantages of high cost and long design cycle when using traditional ASIC chips. It brings revolutionary changes to the traditional simulation system, and its performance is similar to FPGA in the digital system.
At present, ISPPAC series products include 3 kinds of ispPAC10, ispPAC20 and ispPAC80.
The following is a combination of ispPAC to discuss the application of ISP technology in the design of analog systems.
The architecture of 4.1ispPAC
Using ISP technology, lattice company's ispPAC products support 3-dimensional programmable capability: Programmable functions (ampliflcation,conversion,filtering L programmable Characteristics (Gain,bandwidth,oeket,thresholds) and Programmableinterconnect (Reconngumblearchitectums). That is, in addition to the internal physical level of the chip Interconnect programmable, each unit (cell) of the function and characteristics are programmable. Thus, the chip can easily realize the fast programming, erasing and the reconfiguration of the success of the circuit in the condition that the welding state on the printed circuit board remains unchanged.
The basic function unit of ISPPAC device is pacell with special structure, such as instrument amplifier, operational amplifier, filter and other analog circuit unit, composed of several Paceil to simulate function module Pacblocks, the whole chip is composed of several pacblocks. Basic analog functions such as precisionfi1tering, summing/diekrmeing, gain/attenuation and conversion can be realized without the need for resistors, capacitors, etc. At the same time, these basic simulation functions can be flexibly combined to configure and design a more complex simulation system.
such as using ispPAC80, users can in a few seconds within a small chip IC configuration tens of thousands of different five-order precision filters.
4.2ispPAC development environment and ISP programming in system
Lattice company ISPPAC development system Pac-desiger software for designers to provide a graphical style of user interface, software provides a simulation library and circuit method generator, and built-in simulation and verification tools, in the chip before programming to the design of analog circuit simulation, generate a variety of curve reports, Thus greatly simplifying the design experiment and saving the development time.
ispPAC through the lattice company's ispdonwload cable download cable to achieve the ISP system programming, instant can complete the device reconfiguration and reprogramming.