SystemVerilog testbench Study Summary (LAB1)

1. Ntb_template-t Router router.v execute the command generates 3 files (router.v is dut in command)

A, Router.if.vrh, contains the direction of the signal port (relative to the DUT), bit width, this signal can be added to the type (logic or bit), remove the direction, as a signal in the interface declaration. This signal is removed from the bit width as the clocking module in the interface of the synchronous signal Declaration;
B, router.test_top this file will produce a simulation clock signal, interface examples and other signals, the simulation clock can be copied directly to the test harness file use, the example of a copy after a few modifications can be used;

2, Interface
A, in interface, the direction of the signal is specified:
Sync signal: In a clocking block
Asynchronous signal: In a Modport

b, a interface should include: (below example)

1 InterfaceRouter_io (input bit clock);//synchronous signal in interface, introducing clock2Signal Declaration < Type (logic or bit) + bit width + signal name >3 logic reset_n;4Logic [ the:0] DIN;5 ...6 7 //Synchronous Clock Module, actuation and sampling of synchronous signals8 clocking cb @ (Posedge clock)9 defaultInput #1ns Output #1ns//removing jitter from input and outputTen //signal direction (relative to DUT) + signal name One output reset_n; A output din; - ... - ENDCLOCKING:CB the  - //use Modport to connect the interface and test program, and in the Modport parameter list, include the synchronization signal created by the front lock and the potential asynchronous signal.  - //asynchronous Signal Direction designation -Modport TB (clocking cb,output reset_n);//It is important to note that Reset_n is both a synchronous signal and an asynchronous signal +Endinterface:router_io

3. Test program File:

1Program Automatic test (router. TB rtr_io);//Connect test program with Interface2 3 Initial begin4$display ("This My first SV testbench");5 reset ();6 End7 8 task Reset ();9Rtr_io.reset_n =1'b0;//asynchronous signal, blocking assignmentTenRtr_io.cb.frame_n <=1'b1;//Synchronous signal, non-blocking assignment OneRtr_io.cb.valid_n <=1'b1;//Ibid . A //The blocking assignment and the non-blocking assignment are executed at the same time, finally coming to # #2延时2个时钟周期后拉高reset_n -  -##2Rtr_io.cb.reset_n <=1'B1;//reset_n pull down 2 clock cycles and then pull the high theRepeat the) @ (ROUTER.CB); - Endtask:reset -  -Endprogram:test

4. Test Harness File

1' Timescale 1ns/100ps2 module Router_test_top;3 //clock generation can use Ntb_template to generate clocks in Files4Parameter simulation_cycle = -;5 bit systemclock;6 7Router_io Top_io (Systemclock);//instantiate an interface8Test T (TOP_IO);//connect the interface and TB.9Router Dut (//connect the interface to the DUT.Ten . Reset_n (top_io.reset_n), One . Clock (top_io.clock), A . DIN (Top_io.din), - ... - . Frameo_n (top_io.frameo_n) the ); -  - Initial begin -$timeformat (-9,1,"NS",Ten);//Set time +Systemclock =0; - Forever begin +# (simulation_cycle/2) ASystemclock = ~Systemclock; at End - End -  -Endmodule

5, compile and simulation

Vcs-sverilog-fsdb router_test_top.sv test.sv router_io.sv router.v    // Execute words will generate the executable file Simv  . /SIMV    // execution words can produce simulation results and generate waveform files that need to be saved (described below);

6. Waveform Dump
First waveform file:

$vcdpluson; // Add this sentence vcdplus.vpd file

The second waveform file:

$fsdbDumpfile ("test.fsdb"); // the saved waveform file name is named $fsdbDumpvars (0, router_test_top); // Router_test_top is the signal in which the waveform you want to save is in which file;

SystemVerilog testbench Study Summary (LAB1)