TFT-LCD Driving Method Based on ARM chip S3C2410

Tong qingping, Liu duoren, Xi'an University of Electronic Science and Technology

Introduction

Based on the ARM920T kernel, the arm 203 microprocessor is developed by Samsung. It has a master frequency of up to MHz and is suitable for information appliance, smart phone, tablet, handheld devices, mobile terminals, and other fields. The integrated LCD controller is universal and can be used with most LCD display modules.

Pd064vt5 is an active matrix LCD with amorphous silicon TFT as the switching device. This module includes TFT-LCD display, driving circuit and backlight, and its interface is TTL level. The resolution is 640 xforwardedpixels, and 262 colors can be displayed through 18-bit data signals.

1 LCD controller of S3C2410

The LCD controller in S3C2410 can be used to transmit video data and generate necessary control signals (such as vframe, vline, vclk, and Vm ). The output video data port of S3C2410 is shown in 1 of VD.

 

The LCD Control pins are usually defined as follows:

Vclk: pixel clock signal;

VD []: LCD pixel output port;

VM/vden/TP: AC bias signal (STN)/data enable signal (TFT)/sec TFT source driver data loading Pulse Signal multiplexing port of the LCD driver.

1.1 LCD control register in S3C2410

The LCD control registers of S3C2410 include lcdcon1, lcdcon2, lcdcon3, lcdcon4, and lcdcon5.

1.2 Control Process

As shown in figure 1, the LCD controller in S3C2410 consists of regbank, lcdcdma, vidprcs, timegen, and lpc3600. Regbank has 17 programmable Register Groups and 256x16 color palette memory, which can be used to set the LCD controller. lcdcdma is a dedicated DMA that can automatically transmit video data from the frame memory to the LCD controller, with this special DMA, video data is displayed on the screen without being processed by the CPU; vidprcs can receive video data from lcdcdma and modify it to a suitable data format, then it is sent to the LCD driver through VD [], such as 4/8 single scan or 4 double scan display mode. timegen is composed of Programmable Logic and supports different LCD Driver Interface timing and different rates, timegen is used to generate signals such as vframe, vline, vclk, and VM.

FIFO memory is usually located in lcdcdma. When the FIFO is null or some are empty, lcdcdma requires that data be taken from frame storage based on burst transmission mode and stored in the image data to be displayed, this frame of memory is a buffer zone opened by the LCD controller in Ram. After the transmission request is received by the bus arbitration server in the storage controller, the system memory transfers four words to the internal FIFO. The total size of the FIFO is 28 characters. Among them, the low-level memory ol is 12 words, and the high-level memory Oh is 16 words. The S3C2410 has two FIFO instances, which support the dual scan display mode. However, in single scan mode, only one FIFO (too Oh) is used ).

1.3 TFT controller operation

S3C2410 can support STN-LCD and TFT-LCD, here only introduces its control of TFT-LCD. Timegen can generate control signals for LCD drivers (such as vsync, hsync, vclk, vden, and lend ). These control signals are closely related to the configuration of the lcdcon1/2/3/4/5 registers in the regbank register group. Based on these programmable configurations in the LCD control registers, timegen can generate programmable control signals to support different types of LCD drivers. The generation of vsync and hsync pulses depends on the configuration of the hozval and lineval domains of the LCD-CON2/3 register. The hozval and l Neval values are determined by the LCD screen size:

Hozval = horizontal display size-1 (1)

Lineval = vertical display size-1 (2)

The frequency of the vclk signal depends on the clkval field in the lcdcon1 register. The relationship between vclk and clkval is as follows (the minimum value of clkval is 0 ):

Vclk (HZ) = hclk/[(clkval + 1) x2] (3)

Generally, the frame frequency is the frequency of the vsync signal, it is related to vsync, vb2pd, vfpd, lineval, hsync, hbpd, hfpd, hozval and clkval of lcdcon1 and lcdcon2/3/4 registers. Most LCD drivers need the frame frequency that matches the display. The formula for calculating the frame frequency is as follows:

Frame Rate = 1 {[(vspw + 1) + (vbpd + 1) + (lineval + 1) + (vfpd + 1)] × [(hspw + 1) + (hbpd + 1) + (hfpd + 1) + (hozval + 1)] × [2 × (clkval + 1)/(hclk)]} (4)
 
According to the pd064vt5 parameters and formulas (1) and (2), we can conclude that hozval = 639 and lineval = 479. The values of other major registers are given below.

2 logical sequence of pd064vt5

The time series parameters of pd064vt5 are listed in Table 1. Figure 2 shows the time series of the main operations of pd064vt5. According to the timing requirements, the VM/vden signal can be set as the enab signal of the LCD, And the vclk signal as the nclk signal of the LCD. To obtain an appropriate Vm and vclk waveform, you must set the register value correctly and set the following key register values based on the relationship between the register value and the VM and vclk waveform:

 

Hspw = 10; hbpd = 100; hfpd = 47;

Vspw = 1; vbpd = 37; vfpd = 4

Since the operating frequency of hclk of S3C2410 is mostly around MHz, clkval = 1 can be set according to formula (3.

3 Development of drivers in Embedded Linux

Figure 3 shows the hardware connection circuit between S3C2410 and pd064vts.

When developing the embedded system driver, framebuffer can be used as a driver interface that appears in the linux2.2.xx kernel. The corresponding source file is in the Linux/driver S/Video/directory, and the total abstract device file is fbcon. C. This interface abstracts the display device into a frame buffer. You can regard it as an image that displays memory. However, when frame buffering is used, Linux places the video card in graphic mode.

Based on the above analysis of the main registers of the LCD, the author developed the s3c2410fb Driver Based on the framebuffer mechanism. The following is part of the code for successful debugging. It is used to initialize the display screen and set the value of the LCD control register.

4 Conclusion

After hardware debugging and modification, the clock and compound control signals required by pd064vt5 are successfully obtained at the vclk and Vm pins of the S3C2410 Development Board; at the same time, by modifying the S3C2410 driver in the software and compiling the entire system and writing it back to flash, you can correctly display the static startup screen of the original system after the restart, and the screen is clear and stable, achieved the expected results. This device can be used for display and output devices in Industrial Control and In-Vehicle Communication fields. With an appropriate touch screen, it can also form a convenient and reliable input and output device.