What is an FPGA? FPGA is a field programmable logic array, composed of programmable logic resources (LUT and REG), programmable wiring, and programmable I/O. The basic structure of Xilinx FPGA is the same, but with the development of semiconductor technology, FPGA's logic capacity is more and more rich, faster, embedded more and more hard core, such as: ARM processor, PCIE, Ethernet and so on. In the process technology, Xilinx's 7 Series FPGA uses the UltraScale process, the use of 20nm, Ultrascale+ 16nm, each generation of process resources available, more than the previous generation doubled.
In terms of architecture, the real change in Xilinx architecture is the Advanced Silicon Module block (Silicon Modular block,asmbl) from Virtex-4, ASMBL by using a unique column-based structure, each of which represents a dedicated silicon subsystem, such as logical resources, memory, I/O, DSP, processing, hard IP and mixed signals. This makes it possible to assemble different columns of functionality into a specialized domain FPGA for a specific application category, just like stacked wood, with different column modules for different application areas of the FPGA.
Xilinx FPGAs are SRAM-based lookup table technology, so they need to be reconfigured after power-up. Readings from external nonvolatile memory are loaded into the internal configuration SRAM via the configuration controller. Its components include programmable input/output unit, programmable logic Unit and programmable interconnect resource. and integrates the hard core modules of common functions (such as Bram, Clock Management and DSP).
programmable I/O (Input/ output)
Programmable I/O supports different IO pin configurations: IO standard, single-ended or differential, voltage conversion rate and output strength, pull-up or pull-down resistor, NC impedance (DCI), output delay can be done using iodelay components.
Configurable logic block CLB
Configurable logic blocks are circuits that implement a variety of logic functions. In Xilinx FPGAs, each configurable logic block is comprised of 2 slice. Each slice contains a lookup table, register, carry chain, and multiple selector components. and slice has two different kinds of logic: Slicem and Slicel. The SLICEM has a versatile lut that can be configured as a shift register, or ROM and RAM. Each register in the logic slice can be configured for use by the latch.
Cabling resources are used to connect all the elements inside the FPGA, and the length and process of the connection determines the drive and transmission speed of the signal on the wire. The FPGA chip has a wealth of cabling resources, divided into 4 categories according to the process, length, width and distribution of different locations. The first category is the global cabling resources, for the chip internal global clock and reset/set the wiring; the second is a long-term resource for the completion of high-speed signals between banks; the third type is short-term resources for the logical interconnection and cabling between the basic logic units. The fourth category is distributed cabling resources for proprietary clocks, Reset and other control signal lines.
Clock resources are divided into global clock resources, regional clock resources, and I/O clock resources. (1) Global clock Network is a global cabling resource, it can ensure that the clock signal arrives at each target logical unit delay is basically the same. (2) The regional Clock network is a set of clock networks independent of the global Clock network. (3) I/O clock resources can be used for local I/O serializer/deserializer circuit design. Especially useful for source synchronization interface design.
There are two types of embedded memory for Xilinx FPGAs: dedicated block Ram (BRAM) and a lut that can be configured to be distributed RAM. BRAM (Block RAM) is a dual-port RAM, the number of devices, each Virtex-4 BRAM can store 18Kbit of data, support synchronous read and write operation, two ports symmetrical and completely independent, sharing data, each port can change its bit width and depth as needed. The Bram can be configured as single-port RAM, dual-port RAM, content addressable memory (CAM), and FIFO. Bram provides dedicated control logic to implement synchronous/asynchronous FIFO, where the control logic such as counters, comparators, and status tags will not occupy additional CLB resources.
In FIFO mode, Port A of Bram is a read port and Port B is a write port. The data flow operation is automatic, the user does not have to care about the Bram sequence, when the special application needs to elicit Wrcount and Rdcount. The user needs to detect the full and empty tags. You can set both tag values to be configured to any location within the FIFO address segment.
embedded dedicated Hard core
In addition to the above resources and function modules, the FPGA also has the clock management tile (MMCM): Digital clock Management Module (DCM) and phase matching clock divider (pcmd), DSP module and so on. The DSP module provides high-performance, low-power computing units. It enables multiplication-accumulation units. A dedicated transceiver module is also available to implement the serializer/Deserializer (SerDes) functions, such as the Rocketio module, the Ethernet module (Ethernet MAC) module, and the arm core.
In short, with the internal resources of the FPGA will become more and more rich, not only in the original network, telecommunications, medical, industrial and other fields have a wide range of applications, but also in the data center, cloud computing and other new fields to expand the soil.
 Basic structure of the FPGA: six major components of the introduction.
 asmbl-innovative next-generation platform FPGA. Http://www.laogu.com/wz_23841.htm
 Evgeni Stavinov. The 4th is the FPGA structure. FPGA Master Design. Electronic industry Press. 2013, 10.
Xilinx FPGA architecture