Xilinx FPGA high-speed serial transceiver Introduction

Source: Internet
Author: User
Tags gtx

1 overview

Compared with the traditional parallel implementation method, the design based on serial I/O has many advantages, including: less pin count, lower board space requirement, less PCB layer, easy PCB design, smaller connector, lower EMI and better anti-noise capability.

2 technology used in high-speed serial communication 2.1 multi-phase

The secret of high speed lies in the multi-phase technology. the so-called multi-phase, is the different phase of a clock to extract data, for example, by the phase-locked loop to produce a plurality of different phases of the homologous clock, the phase is 0°, 90°, 180°, 270°, using these clocks respectively to the serial data stream sampling, and then by 0 phase clock synchronization, Finally, the parallel data output is converted to realize the high speed clock data of low speed clock processing. If the input serial data stream bit rate is X, then the bit rate of the parallel data stream becomes X/4.

2.2 Line Code 2.21 8B/10B encoding
    1. The 8bits data sent is divided into two parts: High 3 bits (recorded as HGF), low 5 bits (recorded as EDCBA), recorded as d.x.y (X for Edcba,y on behalf of HGF), high 3 bits for 3B/4B encoding (recorded as FGHJ), low 5 bits for 5B/6B encoding (recorded as Abcdei).

HGFEDCBA = Abcdeifghj

    1. Definition one: In abcdeifghj , more than 1:0 one is recorded as +2;0 more than 1 one is recorded as -2;1 and 0 as much as 0. Using the + 2,-2, and 03 values indicate the inequality of the data 0 and 1 numbers (disparity).
    2. Definition two: more than 1:0th = +1,0 for this transmission is more than 1st =-1, where Rd is run unequal (Running disparity).
    3. The initial send status of previous RD is defined as-1, then according to the Rules in table 1, the previous RD from the encoding table can be selected from the current data should be sent disparity.
    4. In addition to the 256 d.x.y data that need to be encoded, 12 of the remaining data are used as K-codes: k.x.y, for example: k.28.1, k.28.5, and k.28.7 called "comma symbols".

The 8b/10b (64b/66b, 128b/132b) encoding technology guarantees DC balance in the transmit data channel, reduces the DC component in the differential signal, and easily recovers the clock at the receiving end.

2.3 Send pre-emphasis

Because the transmission line has the nature of the low-pass filter, the high-speed signal in the circuit board transmission will show noticeable attenuation, especially the effect of skin effect and dielectric loss. The signal edge slope on the transmission line slows down, the code element becomes wider, the amplitude decreases, and the jitter increases, causing the eye pattern to close and the error rate to rise.

Pre-emphasis circuit will signal a certain amount of over-driving, increase the high-frequency components of the signal, after transmission line can still maintain the characteristics of the standard signal, improve the quality of the eye image, reduce the error rate.

2.4 Receive equalization

In addition to the use of pre-emphasis or de-emphasis technology at the transmitting end, the receiving equalization technique is used to improve the system performance.

The frequency characteristic of the receiving equalizer is exactly the opposite of the transmission line, by amplifying the high-frequency signal of the signal, keeping the low-frequency signal, to compensate the transmission line attenuation of the signal, improve the performance of the eye graph and guarantee the transmission quality.

3 Xilinx FPGA Transceivers3.1 system Architecture

The 7 Series FPGAs GTX and GTH transceivers is power-efficient transceivers, supporting line rates from $ MB/s to 12.5 GB/s for GTX transceivers and 13.1 Gb/s for GTH transceivers. Four Gtxe2_channel Primitives and one Gtxe2_common primitive to be a Quad.

The TX rx of the GTX transceiver is independent of each other, but is made up of the PMA (physical media Attachment, physical media adaptation layer) and PCs (physical Coding sublayer, Physical coding sub-layer). The PMA incorporates high-speed serial and conversion (Serdes), pre-emphasis, receive equalization, clock generators, and clock recovery, and the PCs are internally integrated with 8b/10b codecs, elastic buffers, channel bindings, and clock corrections.

3.2 TX

OOB : out-of-band/ side band Signal;

Piso:parallel in Serial out/;

3.21 8b/10b ENCODER/8B/10B Encoder

8B/10B is a industry standard encoding scheme, that trades, bits overhead per byte for achieved dc-balance and bounded Disparity to allow reasonable clock recovery. The transmitter end of the high-speed transceiver is usually equipped with a 8B/10B encoder. The goal is to ensure that the data has enough switching to provide a clock recovery circuit, and the encoder also provides a way to align the data to the word, while the line can maintain a good DC balance. In the GTX application, if the D code is sent, the Txcharisk will need to be pulled low, and if it is a K code, the corresponding Txcharisk will be pulled higher.

3.22 Pattem Generator/prbs Generator

Pseudo-Random bit sequences (PRBS) is commonly used to test the signal integrity of high-speed links. The GTX has a pseudo-random sequence generation circuit, the pseudo-random sequence is seemingly random, but it is a regular periodic binary sequence, there is good randomness and close to the white noise correlation function, so pseudo-random sequence can be used to do bit error rate measurement, time delay measurement, noise generator, communication encryption and spread spectrum communication and other fields, The GTX can be used to test the ber of high-speed serial channel transmissions.

3.23 TX Phase Adjust fifo/phase adjustment FIFO

We all know that FIFO has the function of isolated clock domain, here is no exception, we can know that TX buffer is connected to two different clock domains xclk and TXUSRCLK, in the sending end of the PCS sub-layer contains two clock domains, XCLK (PMA parallel clock domain) TXUSRCLK clock domain, in order to stabilize data transmission, XCLK and TXUSRCLK must be rate matching, phase difference can be eliminated, TX buffer is mainly used to match the rate of two clock domains and eliminate the phase difference between the two clock domains.

3.24 TX polarity control/transmit polarity control

The TX send side supports polarity control of the data sent by TX, and the encoded data output from the PCS sub-layer is reversed before entering the piso serialization, which is mainly used to compensate for PCB design errors, if the PCB design inadvertently txp and Txn cross connection, The polarity of the signal can be flipped by setting the txpolarity to "1".

3.3 RX

EQ : equalizer/ Equalizer;

OOB : out-of-band/ side band Signal;

CDR : Clock and Data recovery/ clock recovery;

SIPO : Serial in Parallel out/ string in and out;

3.31 RX Equalizer (DFE and LPM)/equalizer

After the RX signal comes in from the analog front end, first through the RX equalizer, the main function of the equalizer is to compensate for the signal in the channel transmission process of high-frequency loss, because the channel is limited bandwidth, so the signal through it will cause attenuation and even destroyed. The RX receiver has two equalizers, LPM and DfE, which differ in power consumption and performance, where the LPM consumes less power and the DfE provides more accurate filter parameters to better compensate for transmission channel losses and therefore better performance.

3.32 RX cdr/Clock Recovery

Since the GTX transmission does not carry the on-road clock, the receiver must do its own clock recovery and data recovery, first the external data comes in after the equalizer, and then the equalizer comes out of the data into the clock data recovery circuit. The GTX uses a phase-rotated CDR structure, the data coming from the DfE is captured by the edge sampler and the data sampler, and then the CDR state machine determines the phase of the data stream and the feedback control phase interpolator (PI), when the location of the data sampler is located in the center of the eye, and the edge sampler locks into the data stream's transmission domain. The CPLL or QPLL provides the basic clock for the phase interpolator, which makes the CDR state function very good for phase control.

3.33 RX polarity control/receive polarity control

As with the TX transmitter, the RX receiver also has a polarity control function that can be used for data rollover, which is used when the RXP and Rxn are reversed during PCB design.

3.34 RX Comma Detect and align/k code detection and alignment

Before the serial data is parallelized, it is necessary to find an appropriate feature boundary, which is a recognizable sequence sent by the TX sender, usually called an identifier (comma) or a K-code, and the receiving end searches for the identifier in the incoming data, and when the identifier is found, The data received later has this identifier for the boundary to Parallelize, and how it works.

3.35 RX PRBS checker/prbs Checker

The GTX contains an inline PRBs checker, shown in 4, with four different pseudo-random sequence generators to choose from, and the checker is self-synchronizing and works before boundary alignment and decoding, which can be used to test signal integrity.

3.36 RX Elastic buffer/receive elastic buffers

Rx Receive-side elastic buffers are an important feature, compared to TX receive-side buffering, Rx has a "flex" attribute, which means that the RX elastic buffers have more features (Rx clock correction and RX-channel binding) than the TX transmitter.

3.37 RX clock correction/clocking correction

The "elasticity" of the RX elastic buffer is reflected in the frequency difference that can be adjusted by the clock correction to XCLK and RXUSRCLK. For RX receivers, even if the XCLK and RXUSRCLK run at the same clock frequency, but there are often differences, this difference can easily lead to the RX elastic buffer full or read empty, clock correction function came into being.

Generally speaking, at the TX send side, we will periodically send K code to ensure that the receiving end of the boundary alignment, in the RX elastic buffer when the data is insufficient, the received K code data will be copied to the RX elastic buffer to keep the RX elastic buffer half full. When the RX elastic buffer data is too high, the received K-code data will be discarded and not written to the RX elastic buffer to keep the RX elastic buffer half full.

3.38 RX channel bonding/channels binding

The channel binding function also embodies the "elasticity" of the Rx elastic buffer, and for protocols such as PCIe and Srio, multi-lane transmission can be supported to increase the total bandwidth of the transmission. Because of the transmission channel, the data sent at the same time by the TX sender cannot be received by all lane at the same time at the RX receiver, and each lane receives a time difference, so it is re-aligned when the data is recovered, so the channel binding function needs to be performed on the RX receive side.

To achieve this function, the TX sender adds an identical channel binding sequence to the transmitted data stream, and the RX receiver makes corresponding adjustments and delays in the respective Rx elastic buffers based on the channel binding sequence detected by each lane, eventually making the data in each lane non-existent, in the FPGA RX The output of the interface can be the same as the data sent by the TX sender, with misaligned data on the left and aligned data on the right.

4 Examples of 4.1 GT types

4.1 GTX configuration (Xilinx ZC706)

The ZC706 board provides access to the GTX transceivers:

? Four of the GTX transceivers is wired to the PCI Express x4 endpoint Edge connector (P4) fingers

? Eight of the GTX transceivers is wired to the FMC HPC Connector (J37)

? One GTX transceiver is wired to the FMC LPC Connector (J5)

? One GTX transceiver is wired to SMA connectors (rx:j32, J33 tx:j35, J34)

? One GTX transceiver is wired to the sfp/sfp+ Module Connector (P2)

? One GTX transceiver is unused and are wired in a capacitively coupled TX-TO-RX loopback configuration

4.2 Ibert Eye Chart

Test the GTX transmission channel quality using the Xilinx IBERT (Integrated Bit Error Ratio Tester) IP.

Figure 1 Pin Direct connection

Figure 2 SMA pin loopback (not tightened)

Figure 3 SMA pin Loopback (tightening)

6 References
    1. http://xilinx.eetrend.com/blog/10730;
    2. http://xilinx.eetrend.com/blog/10745;
    3. Xilinx 7 Series FPGAs gtx/gth transceivers User guide UG476 (v1.12) December 19, 2016;
    4. Xilinx Integrated Bit Error Ratio Tester 7 Series GTX transceivers v3.0 LogiCORE IP Product guide Vivado Design Suite PG13 2 June 8, 2016.

Xilinx FPGA high-speed serial transceiver Introduction

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