Xilinx TCL script without Gui

How to creat a Xilinx TCL script without Gui? Try the following example:

Project New my_proj1.ise
Project set family spartan3e
Project set device xc3s500e
Project set package fg320
Project set speed-4

######################################## #######################################
# Modify the XFile add argument for the source files in the Design
######################################## #######################################

Puts "adding source files ..."
XFile Add ../src/dice. vhd
XFile add temp. UCF

######################################## #######################################
# Set optional implemenation options here. There is a problem with setting
# Project properties that at least one source must be added to the project
# First. Therefore, the "Project set" commands are after the "XFile Add"
# Commands.
######################################## #######################################

Puts "setting project properties ..."

project set "Custom compile file list" "fpga_ B .prj"
project set "optimization effort" high
project set "cores search directories ".. /src
project set "read cores" true; # default is true, don't need to set
project set "macro search path ".. /src
project set "map effort level" high
project set "perform timing-driven packing and placement" 1
project set "Place & Route effort level (overall) "High
# do not generate the default post place static timing Report
project set" generate post-Place & Route static timing Report "false

######################################## #######################################
# Run the design.
######################################## #######################################

Process Run "Implement Design"
Puts "implement design done"
Process Run "generate programming file"
Puts "bit file ready! "

Project Close

Puts "project closed! "

(From: http://forums.xilinx.com/xlnx/board/crawl_message? Board. ID = ise & message. ID = 1186)