FPGA read and write operation of asynchronous SRAM

Asynchronous SRAM: As its name does not run synchronously with a particular clock signal, it runs according to the state of the input signal. Since there is no signal indicating that valid data has been identified at the time of reading, and there is no signal that the data has been received at the time of writing, it is necessary to obtain the manufacturer's data sheet, according to the timing diagram, the "should have read the valid data" and "should be able to receive data" conditions such as memory design.

1. Read operation: OE read controlthe basic read operation of asynchronous SRAM is shown in 1. first specify the address, then make the ce2=we= high, ce1=oe= Low, at which point the data will appear on the I/O pin. If you change the address while maintaining the state, the data for the new address appears. In addition, if the ce1,ce2,we and OE do not meet the condition of the read state, then the SRAM aborts the drive I/O pin to high impedance. 　Figure 1 Read operation of asynchronous SRAMRead operation, so that Ce1,ce2,we,oe and so on to maintain the read state, also allows to change the address (that is, to maintain access to the state, only change the address, read the data of different addresses). However, part of the high-speed SRAM also exists, that is, when the device is in the selected state (CE effective), if the address is changed, the device to determine the wrong operation, so beforehand need to confirm whether to allow such an application.2. Write operation 1:we Write controlthe basic write operation for asynchronous SRAM is shown in 2. first specify the address, if the ce2= high, ce1= Low, the device is in the selected state. as long as OE is active (low), at this point SRAM temporarily outputs data. However, since we have priority, once we are active, the I/O pin becomes a high impedance state and the SRAM no longer outputs data. the address of the write operation must be determined before the OE drops, and the data write operation is performed on the We rising edge.

Figure 2 write operation for asynchronous SRAM 1 (we write control)

3. Write Operation 2:ce Write control

The CE write control is shown in Operation 3. Ce write control writes data using CE1 and CE2 in a state where Li is already in effect. Since we are already valid, the device becomes a select state and also becomes a write state.

Figure 3 write operation for asynchronous SRAM 2 (CE write control)

You can also refer to the following links http://www.cnblogs.com/sunev/archive/2011/10/31/2229973.html

FPGA read and write operation of asynchronous SRAM