High-Speed PCB design based on signal integrity analysis

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Introduction

Signal integrity refers to the signal quality in the circuit system. If the signal can be sent from the source end to the receiving end without losing sight within the required time, it is called that the signal is complete. With the rapid development of semiconductor technology, the output speed of IC switches is improved, and the signal integrity problems (including signal overshoot and underloading, ringing, reflection, crosstalk, and ground play) it has become one of the important issues in High-Speed PCB design. Generally, the frequency of a digital logic circuit reaches or exceeds 50 MHz, and the circuit working at this frequency occupies more than 1/3 of the entire system, it can be called a high-speed circuit. In fact, compared with the frequency of the signal itself, the harmonic frequency of the signal edge is higher, and the hop (rising and falling along) of the rapid signal changes lead to the unexpected effect of signal transmission. This is also the root cause of the signal integrity problem. Therefore, it is necessary to consider how to fully consider the signal integrity factors in the high-speed PCB design process and take effective control measures to improve the circuit design quality.

The powerful Cadence speectraquest simulation software and the IBIS model are used to simulate and analyze the signal integrity of High-speed signals, which is an efficient and feasible method to detect signal integrity problems, optimize the Design Based on the simulation results on issues related to signal integrity, so as to improve the design quality and shorten the design cycle.

1. Application Design Example

The function of the control unit designed in this paper is to transmit the encoding signal received by the ground receiving device to the data processing center of the main station. The specific process is to first store the data of the upper computer, and then use the bit error rate test and calculation to select a path with the lowest Bit Error Rate as the data transmission path, finally, the stored host computer data is transmitted to the master station data processing center for processing. After comprehensive consideration, the cyclone II-2C8 of Altera Company is selected as the core chip, as well as external extended SDRAM, Flash, various input/output circuits and maxcompute interface chips, etc, it is also implemented in conjunction with the development kit of the niosii software core processor. The control unit structure 1 is shown.

CycloneII-2C8 clock frequency as high as 150 MHz or above, because FPGA internal data storage area is relatively small, so the use of SDRAM extended external data storage space. SDRAM uses hy57v651610/so from hy-Nix, and the clock frequency is above 75 MHz. Therefore, the signal integrity problem caused by high signal frequency must be considered. A powerful CAD-ence design software is selected, which integrates schematic design, PCB layout, and high-speed simulation analysis, it can solve the problems related to electrical performance in all aspects of the design, greatly improving the design success rate.

2 Key Signal topology and Simulation

The high frequency of the system is FPGA and SDRAM. The clock frequency of FPGA can reach more than 150 MHz, and that of SDRAM can reach more than 75 MHz. Because the Internal High Frequency of FPGA does not affect other devices, and the connection between FPGA and SDRAM is seamless, the signal integrity directly affects whether FPGA can correctly read and write the SDRAM. In PCB design, the high-speed simulation tool specctraquest of the Caden-CE software is used, and the IBIS model of the device is used to analyze the signal integrity, and the impedance matching and topology structure are optimized, to ensure the normal operation of the system. This article only gives a detailed explanation of signal reflection and Crosstalk. Other simulations are similar.

2.1 reflection

The transmitter is 44 pins of hy57v561620, the receiver is 60 pins of Cyclone II, and the excitation is a square wave of 66 MHz. Figure 2 shows the topology, and Figure 3 shows the simulation waveform.

It can be seen from the simulation waveform that the waveform distortion caused by signal reflection produces a significant ringing phenomenon. The existence of the ringing phenomenon causes logical function disorder when the signal crosses the level logical threshold multiple times. An effective way to reduce the noise of a ring is to concatenate a small resistor in the circuit, which provides damping for the circuit, which can significantly reduce the amplitude of the ring and shorten the time of the vibration, at the same time, the circuit speed is almost unaffected. In engineering use, the resistance is usually 33 Ω. Topology Structure and simulation waveform 4 and figure 5 after the series resistance are shown.

In fact, this solution is called impedance matching, which plays an extremely important role in signal integrity.

2.2 Crosstalk

Extract sd_dqlo (59 Pin connected to Cyclone II and 45 pin of hy57v561620), sd_dqll (connect 58 pin of Cyclone II and 47 pin of hy57v561620 ), SD_DQ-l2 (48 pins connected to cycloneii and hy57v561620) these three networks perform Crosstalk Simulation between them. Among them, sd_dqll as the attacked network, sd_dqlo and SD_D-Ql2 as the attack network. Their topology and simulation waveforms 6. Figure 7 (parallel coupling length of transmission lines L = 1000 mil, spacing P = 5 mil ).

The simulation waveform 8 is shown. Figure 7 shows that crosstalk has a great impact on the attacked network. The crosstalk value crosstalk = 657.95 is related to the parallel coupling length of the transmission line and the spacing p, the shorter the coupling length, the larger the spacing, the smaller the crosstalk. The simulation results are listed in Table 1.

Therefore, when making a PCB, the parallel length between different signal lines should be minimized, the spacing between them should be widened, and the line width and height of some lines should be changed. Of course, there are many factors that affect crosstalk, such as the current flow direction and the rising time of the signal frequency of the interference source.

Conclusion

In this high-speed PCB design of the control unit, the use of powerful Cadence software, from creating a schematic diagram, PCB layout to high-speed simulation analysis, achieved good results. The reasonable topology and layout and wiring obtained by the speectraquest simulation analysis can make the circuit board work normally. This design greatly shortens the hardware debugging time, improves work efficiency, and saves design costs.