How to solve the problem of FPGA high fanout

Fanout, that is, fan-out, refers to the module directly called the number of sub-modules, if this value is too large, the FPGA directly displayed as net delay is larger, not conducive to timing convergence. Therefore, you should try to avoid high fan-out when writing code. However, in some special cases, the need of the overall structure design or the inability to modify the code constraints, you need to solve the problem of high fan out through other optimization methods. Here are three ways to do this:

First of all, the following example, as shown in Figure 1 is a transpose FIR filter in the critical Path timing report, in the FIR of DSP in FPGA has introduced the rotary structure FIR filter input data of large fan-out, shown in Figure 1 is 11, so net delay up to 1.231ns. As shown in Figure 2, the input data drives 11 dsp48e1.

In the absence of optimization, the Fmax:206.016mhz of the design

1. Register copy

Register replication is one of the most common methods of solving high fan-out problems by replicating several identical registers to share the task of driving all modules from a single register, thereby reducing fan-out. By simply modifying the code, as shown in Figure 3, 4 registers were copied: din_d0, din_d1, Din_d2, Din_d3,din_d, din_d0, DIN_D1, DIN_D2 Drive 2 dsp48e1,din_d3 drives 3 dsp48e1 respectively. In the code, in order to prevent the synthesis of the same register, the corresponding signal is added (* equivalent_register_removal= "NO" *) attribute to avoid being optimized.

After the comprehensive implementation of the timing report as shown in Figure 4, the data path on the input data fanout minus 2, the corresponding net delay also reduced to 0.57ns. The resulting design, as shown in Figure 5, replicates 4 registers to share the fanout, as expected. Get Fmax:252.143mhz after register optimization

2. Max_fanout Properties

In the code can set the signal properties, the corresponding signal Max_fanout property set to a reasonable value, when the actual design of the signal fanout more than this value, the integrated device will automatically use the optimization of the signal, the common means is actually register copy. The properties are set as shown in the following code:

(* max_fanout = "3" *) Reg signed [15:0] Din_d;

The Max_fanout property of the Din_d signal is set to 3, after a comprehensive implementation, the timing report is shown in Figure 6, where fanout only 2, the corresponding net delay is only 0.61ns, automatic optimization effect is good. The structure is shown in Figure 7, where din_d_12_1, din_d_12_2, and Din_d_12_3 are automatically added after the optimization of the synthesis, that is, the Register copy function is realized. Get Fmax:257.135mhz after setting max_fanout property optimization

3. BUFG

Usually the BUFG is the resource used for the global clock, which solves the problem caused by the high fan out of the signal. But it is generally used for clocks or resets, such as the super-large signal, such signals involved in the logic of the entire chip, and BUFG can be a global perspective to optimize cabling. And a piece of FPGA chip BUFG resources are also limited, on the 7k325tffg900 also only 32, if used for ordinary signal high fan out optimization is not realistic. Therefore, it is necessary to use BUFG on the clock, but if the design encounters some timing problems due to the high fanout of the reset signal, it can be optimized using BUFG on this signal.

In general, in the case of high signal fan out, the common signal can be used to copy the register or set the Max_fanout property optimization, and for the reset signal, can be added BUFG optimization.