[Iboard electronic school tutorial] [stm32 read and write FPGA example through FSMC]

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I. ArmProgramIntroduction

1.Write Functions

 
1 # DefineFpga_write (offset, data) * (volatile unsigned short int *) (cs0_base + (offset <17) = Data
 

Where:

• Offset is the space offset in the range of 0 ~ 7 (8 spaces );
• Data is a 16-digit integer with a range of 0 ~ 65535;
• Cs0_base is the base address of the FPGA CS0 connected to arm. For details, see the schematic.

If 1234 is written to space 2, the call method is:

 
1Fpga_write (2,1234);
 

1.Read Functions

 
1 # DefineFpga_read (offset) * (volatile unsigned short int *) (cs0_base + (offset <17 )))
 

Where:

• Offset is the space offset in the range of 0 ~ 7 (8 spaces in total );
• The value range is a 16-bit certificate. The value range is 0 ~ 65535;
• Cs0_base is the base address of fpgacs0 connected to arm. For details, see the schematic.

To read the value of space 2, call the following method:

1UnsignedShort IntRead_data;2 3Read_data = fpga_read (2);
 

 

II. Introduction to FPGA Program

The figure below shows FSMC.CodeThe generated top-level module connection, where:

• DB [15 .. 0] AB [18 .. 16] WR RD CS0 is connected to arm;
• Led_fpga uses outg [0] to control its brightness and elimination (you can control it through the panel );
• Ina [15 .. 0] ~ INH [15 .. 0] is the input for reading data. It contains 8 spaces, each of which has 16 digits;
• Outa [15 .. 0] ~ Outh [15 .. 0] is the write space register, with 8 spaces in total, each with 16 bits;

For specific implementation principles, see FSMC. V program.

 // FSMC read/write ep4ce6 demo  Module  FSMC (AB,  //  Address DB, //  Data WRN, //  WR Rdn, //  Rd Resetn, //  Resetn CSN, //  CS Ina, //  Input data INB, //  Input data B INC, //  Input data c IND, //  Input data d INE, //  Input data E INF, //  Input data F ING, //  Input data g INH, //  Input data H Outa, //  Output Data Outb, //  Output Data Outc, //  Output Data Outd, //  Output Data Oute, //  Output Data Outf, // Output Data Outg, //  Output Data Outh //  Output Data  );  Input [ 2 : 0  ] AB;  Inout [ 15 : 0  ] DB;  Input WRN;  Input  Rdn;  Input  Resetn;  Input  CSN;  Input [ 15 : 0  ] Ina;  Input [ 15 : 0  ] INB;  Input [15 : 0  ] Inc;  Input [ 15 : 0  ] Ind;  Input [ 15 : 0  ] INE;  Input [ 15 : 0  ] INF; Input [ 15 : 0  ] Ing;  Input [ 15 : 0  ] INH;  Output   Reg [ 15 : 0  ] Outa;  Output   Reg [15 : 0  ] Outb;  Output   Reg [ 15 : 0  ] Outc;  Output   Reg [ 15 : 0  ] Outd;  Output   Reg [ 15 : 0  ] Oute;  Output   Reg [ 15 : 0  ] Outf;  Output   Reg [ 15 : 0  ] Outg;  Output   Reg [ 15 :0  ] Outh;  Wire  Rd;  Wire  WR;  Reg [ 15 : 0  ] Indata;  Assign RD =! (CSN & rdn ); //  Get RD pulse ____ | ~~~~ | ______      Assign WR =! (CSN & WRN ); // Get WR pulse ____ | ~~~~ | ______          Assign DB = RD? Indata: 16  '  Hzzzz;              //  Write Data: select eight spaces to write data based on the address line. Each space is 16 bits.      Always @( Negedge WR Or   Negedge  Resetn)  Begin          If (! Resetn) Begin Outa <= 16  '  H0000; Outb <= 16  '  H0000; Outc <= 16  '  H0000; Outd <= 16  '  H0000; Oute <= 16  ' H0000; Outf <= 16  '  H0000; Outg <= 16  '  H0000; Outh <= 16  '  H0000;          End      Else    Begin          Case  (AB) 3  '  B000: outa <= dB;              3  '  B001: outb <= dB;              3  '  B010: outc <= dB;              3  '  B011: outd <= dB;              3  '  B100: oute <= dB;              3  ' B101: outf <= dB;              3  '  B110: outg <= dB;              3  '  B111: outh <= dB;              Default  :;  Endcase          End      End                      //  Read data selects 8 spaces for reading based on the address line. Each space has 16 digits.      Always @ (Rd Or !Resetn)  Begin          If (! Resetn) indata <= 16  '  H0000;          Else    Begin          Case  (AB)  3  '  B000: indata <= ina;              3  '  B001: indata <= INB;             3  '  B010: indata <= Inc;              3  '  B011: indata <= ind;              3  '  B100: indata <= INE;              3  '  B101: indata <= inf;              3  '  B110: indata <= ing;              3  ' B111: indata <= INH;              Default  :;  Endcase          End      End      Endmodule   

 

Iii. Function Testing

 

As shown in, in FPGA, put outh [15 .. 0] output data. Connect to INa [15 .. 0], the arm program will write space 7 (that is, outh [15 .. 0]), and then read the space 0 (that is, INa [15 .. 0]), and then perform non-validation of the data to determine whether the data is successful or not. A total of 65536 tests were conducted for 300 tests per round. The core code is as follows:

For(I =0; I <65536; I ++) {Fpga_write (7, I); dat= Fpga_read (0);If(DAT + I )! =65535) {Errors++;}ElseSuccess ++;}
 

 

4. Software Interface

The Interface contains four buttons. Press Start test to perform a read/write test. During the test, press stop test to stop the test. Press Light Emitting tube to display the LED controlled by FPGA, light Emitting Diode: The Light Emitting Diode controlled by FPGA.

 

 

 

 

 

 

 

 

Download the software package and PDF file:

Http://files.cnblogs.com/xiaomagee/iboard_fsmc_pub.zip