Introduction to OpenRISC (7) based on or1200 minimum SOPC system (i)

Erection and Simulation (DE2,DE2-70)

I recently got OpenRISC, someone was working on it, and wrote a master thesis, I've uploaded:

http://download.csdn.net/detail/rill_zhen/5303401

The following content should be based on the guidance of the paper completed, but not my completion, so reproduced as follows:

Do a or1200 minimum system, Or1200+wishbone+ram+gpio, on the DE2 platform to read the value of the SW and then LEDR to show the simple program. I'll record some of the major steps.

In opencores download source or1200-rel1.tar.bz2,wb_conmax_latest.tar.gz, gpio_latest.tar.gz extract source code to or1200, Wb_conmax, Gpio directory.

In addition, a onchip-memory and clock-providing PLL for the system is needed, generated using the Altera Megawizard Plug-In Manager tool.

The generation of RAM (original) Altera 1-port ram Wishbone Slave interface notation and wishbone Master BFM authentication, in this article, is initialized with a ram0.mif file (the build method is described below).

The configuration of the PLL is as follows

Inclk0 50M

Clk c0:output clock Frequency:25mhz, clock phase shift 0.00 NS, clock duty cycle%:50

Provide clocks for or1200

Clk c1:output clock Frequency:10mhz, clock phase shift 0.00 NS, clock duty cycle%:50

The generated directory structure

/or1200_sopc

/or1200

/wb_conmax

/gpio

/ram

/pll