Learning timer based on stm32f103zet6 1 (theoretical knowledge)

I heard a netizen say that the timer is complicated and difficult to implement. A student in the lab also worked on it for a while, but what kind of research type does it belong! I also came to the timer chapter.

I checked it online and read some books, advanced timer, general timer, and general timer. Let's start learning from general timer!

I. First, let's break down the timer block diagram. the suffocating block diagram is really scary! Although suffocated, it is still necessary to paste it!

The register name in the above diagram is explained as follows:

TIMx_ETR: TIMER External Trigger pin ETR: External Trigger input ETRP: External Trigger input after dividing ETRF: External Trigger input after filtering

ITRx: edge detector that triggers x internally (triggered by another timer) TI1F_ED: TI1. TI1FP1/2: input of the timer 1/2 after filtering TRGI: trigger Input

TRGO: trigger output CK_PSC: it should be called the divider clock input CK_CNT: timer clock. (The calculation of the scheduled cycle depends on it)

TIMx_CHx: TIMER input foot TIx: it should be called the TIMER input signal xICx: Input comparison x ICxPS: After dividing the ICx

OCx: Output capture x OCxREF: Output reference signal

1. the main part of the universal timer is a [16-bit counter] and its related [automatic loading register ].

Three counting methods can be implemented:

A. [increase count]

B. [count reduction]

C. [increase or decrease the count at the same time] (note that while understanding the count here, we should not be at the same time)

The description of the count mode on datasheet is as follows!

In the up-counting mode, the counter starts counting from 0 to automatically loading the value (the content of the TIMx_ARR counter), and then starts from 0 again.
Counts and generates a Counter Overflow Event.

In downward mode, the counter starts counting down from the automatically loaded value (the value of the TIMx_ARR counter) to 0, and then
The loaded value restarts and a Counter Overflow Event is generated.

In central alignment mode, the counter starts counting from 0 to automatically loaded value (TIMx_ARR register) −1 to generate a counter
Overflow Event, then count down to 1 and generate a Counter Overflow Event; then count again from 0.

I don't know much about the central alignment mode. My personal understanding is that if the initial value is 3, the counting method is

3, 2, 1, 0, 1, 2, 3, advanced-1 operation, then perform + 1 operation!

Finished!

2. First, we should introduce the clock unit: What is the timer providing the clock cycle?

Let's take a look at several clock modes:

The counter clock can be provided by the following clock sources:
· Internal clock (CK_INT)
· External clock Mode 1: external input foot (TIx)
· External clock Mode 2: External Trigger input (ETR)
· Internal trigger input (ITRx): use one timer as the pre-divider of another timer. For example, you can configure one timer Timer1 as the pre-divider of another timer Timer2.

Because the timer function is too powerful, the internal clock mode is used. Let's talk about other functions! I can't help it! So what is the internal clock mode ??

Take a picture from the Internet and you will be quite clear.

TIM1 and TIM8 are provided by APB2, while the TIM2--TIM7 is provided by APB1. From the clock source, can we guess that timer 1 and timer 8 are more advanced?

APB2 provides up to MB! At least I guess so! Intercept a netizen's explanation of the timer clock settings. If you read the timer, you will be very clear. I have sorted out his words!

1. We can see that the timer clock is not directly from APB1 or APB2, but from a frequency divider with the input of APB1 or APB2. In the blue part of the figure, note that it is a frequency divider, not a frequency divider, continue reading !!

2. The following uses the Timer 2 ~ The clock of 7 illustrates the role of this frequency multiplier: (of course, the timer and timer 8 are also like this)

A. When the pre-division coefficient of APB1 is 1, this frequency divider does not work (that is, the frequency doubling coefficient is 1), and the timer clock frequency is equal to the frequency of APB1;

B. When the pre-division coefficient of APB1 is other values (I .e., the pre-division coefficient is 2, 4, 8 or 16), this frequency divider works, the timer clock frequency is twice the frequency of APB1 (the multiplier coefficient is 2 ).

3. These examples can be used to describe (for Timer 2 to timer 7)

A. Assume that AHB is 36 MHz. Because the maximum frequency allowed by apb1 is 36 MHz, the pre-division coefficient of apb1 can be any number;

B. When the pre-division coefficient of apb1 is 1, apb1 = 36 MHz, tim2 ~ Clock frequency of 7 = 36 MHz (the multiplier does not work); when the pre-division coefficient of apb1 is 2, apb1 = 18 MHz, tim2 ~ The clock frequency of 7 is 36 MHz.

Summary: Some people may ask, since tim2 ~ If the clock frequency of 7 is 36 MHz, why not directly use the pre-division coefficient of apb1 = 1?

The answer is: apb1 should not only be tim2 ~ 7 provides the clock and other peripherals also provide the clock. setting this frequency divider can ensure that other peripherals use a lower clock frequency, tim2 ~ 7 can still get a high clock frequency.

Another example: When AHB = 72mhz, the pre-division coefficient of apb1 must be greater than 2, because the maximum frequency of apb1 can only be 36 MHz. If the Pre-division coefficient of apb1 is 2, The tim2 ~ 7 still can get the 72 MHz clock frequency. The higher clock frequency can undoubtedly improve the timer resolution, which is exactly the original intention of designing this frequency divider.

I believe that we can all be familiar with the timer operation, but this is only one of the modes, that is, the internal clock mode!

There are three other models that will not be discussed for the moment.

3. After having a rough understanding of the clock, continue to look at a difficult point.

The so-called register with shadow comes out, and the five registers with Shadow do not exist. Do not think it is a problem of printing or scanning, let's take a look at the general explanation of this shadow register: Shadow registers indicate that this register corresponds to two registers physically, and one is a register that can be written or read by programmers, it is called preload register (preload register), and the other is a register that is invisible to the programmer but actually works in operations, called Shadow register (shadow register); as mentioned in section 14.3.1 of the manual, according to the Apre bit settings in the timx_cr1 register, the content of the preload register can be transmitted to the Shadow register at any time, that is, the two are connected (permanently), or each update event (uev) the contents of the preload register are transmitted to the Shadow register.
!

Now I understand this feature. My understanding is a complicated automatic reinstallation process. 4. here you must have found the upper-case U and the Small arrow! Let's look at the following analysis: It indicates that the shadow register of the corresponding register can be updated to its preload register content when an update event occurs. In the UI part of the figure, the corresponding Autoreload register can generate an update event (U) or an update event interrupt (UI ).
The so-called time U, the event UI is interrupted! 5. What are the benefits of this design? The benefit of designing preload register and shadow register is that all registers that really need to work (shadow register) can be at the same time (when an update event occurs) updated to the corresponding preload register content. This ensures that operations on multiple channels can be accurately synchronized. If there is no shadow register, or preload
Register and shadow register are passed through, that is, when the software updates the preload register, the shadow register is also updated, because the software cannot update multiple registers at the same time, as a result, the time sequence of multiple channels cannot be synchronized. If other factors (such as interruptions) are added, the time sequence relationship of multiple channels may be unpredictable.
6. Check the timer channel in the lower left corner: the timer input channel of TM32 has a filter unit, which is located on each input channel (the yellow box in) and on the External Trigger input path (in the blue box), they are used to filter out high-frequency interference on the input signal.
The procedure is as follows:

CKD [1:0] In timx_cr1 allows you to set a sampling frequency benchmark for the input signal. There are three options:

1) sampling frequency reference F<sub>DTS = timer input frequency fCK_INT

2) sampling frequency reference fDTS = timer input frequency fCK_INT/2

3) sampling frequency reference fDTS = timer input frequency fCK_INT/4</sub>

Then, the above frequency is used as the benchmark to sample the input signal. When n valid electric signals are continuously sampled, a valid input level is considered.

The actual sampling frequency and number of sampling times can be selected by the user program as needed; the filter parameters of the external triggering input channel are set in the ETF [] of the slave mode control register (timx_smcr; filter parameters for each input channel in capture/compare mode register 1 (timx_ccmr1) or capture/compare mode register 2 (timx_ccmr2) ic1f [], ic2f [], ic3f [], and ic4f.

Note: The injection pin is the same as the output pin !, The previous operations are also described in the Manual! See

For example, when F_{When CK_INT = 72MHz, select fDTS = fCK_INT/2 = 36 MHz, sampling frequency fSAMPLING = fIf DTS/2 = 18 MHz and N = 6, the signal with a frequency higher than 3 MHz will be filtered out by this filter, effectively shielding interference above 3 MHz.}

For example, in combination with the interruption of input capture, you can easily achieve the de-jitter function of keys without the intervention of software. This is a de-jitter function implemented by hardware, this greatly saves software overhead and program code length.

Each timer can input up to four buttons. This method can also be used for keyboard matrix scanning. In addition, the software does not need to scan frequently because it is implemented through interruption.

This article also excerpted a netizen. It was very painful to learn the oscilloscope, so it was not very understandable!

7. Finally, let's talk about capturing channels. This is the core thing!

Each capture/compare channel is centered around a capture/compare register (including the shadow register), including the captured input part.
(Digital filtering, multiplexing, and pre-divider), and output (comparator and output control ). I understand the shadow register!

First, let's look at the block I circled in red, which is a capture comparison channel:

If the input is irrelevant to the encoder, it means that the input of TI can be obtained to the third node, or the input of T2 can be obtained to the third node, in fact, we can also get T1 to B _1 and T1 to CC2 at the same time, so that we can get the PWM input later. The output feature is that there is an OC1REF instead of direct output, so that you can define whether it is highly effective or low, and output the desired effective level!

The above are just some basic and non-comprehensive knowledge about the timer. Next, we will analyze the code to gain a deeper understanding of this timer!

You and I are not finished yet! To be continued ..