Mipi display standard for mobile internet devices

Source: http://www.21ic.com/app/ce/200906/44116.htm

As mobile internet devices become increasingly popular, more and more manufacturers are competing to design the latest and most fashionable products. Low Power Consumption is always the most important thing for handheld devices, including the power consumption of their display components. According to market research firm iSuppli, Intel's processors for these devices account for half of the market. To replace the traditional and outdated RGB parallel bus, Intel used LVDS and mipi DSI bus interfaces in the recently released moorestown processor.

Mipi DSI is the latest display standard for mobile handheld devices. By configuring a Scalable Data Channel, this interface can achieve 3 Gbit/s data transmission rate. It uses low-voltage swing differential signals and has a very low output signal level. ECC and CRC checksum are also embedded in the datagram to allow the acceptor to perform error correction and recovery.

Application developing
Over the past few years, when the mipi DSI and DCS standards have gradually matured, display manufacturers have begun to follow these standards in their own products. Due to the complexity of the hybrid signal design and the uncertainty of increasing market demand, mobile Internet equipment manufacturers can only obtain a few monitors integrated with the mipi interface. Initially, most display manufacturers preferred the New and Old Standard bridging schemes before producing monitors that integrate the mipi functionality, which can convert high-speed serial interfaces into traditional parallel RGB interfaces, to test the market response.

As shown in 1, mipi supports the following two display standards.

Figure 1 (a) mipi video mode schematic diagram (B) mipi DCS command mode Diagram

1 DSI video mode
This working mode is similar to the traditional RGB interface, and the host needs to continuously refresh the display. Because no special data signal is used to transmit synchronization information, the control signal and RGB data are transmitted through the mipi bus in the form of packets. Because the host needs to regularly refresh the display, the display does not need frame buffers.

2. DCs command mode
The mipi bus controller sends pixel data streams to the display using the display command message. The monitor should have a full frame long frame buffer to store all pixel data. Once the data is placed in the frame buffer of the monitor, the timing Controller extracts the data from the frame buffer and automatically displays the data on the screen. The mipi bus controller does not need to regularly refresh the display.

Advantages and disadvantages of the two modes
Each working mode has advantages and disadvantages in terms of cost and power consumption. The video mode display architecture does not require frame buffers. However, the host regularly sends DSI video packets in high-speed mode, which consumes a lot of average energy.

Ideally, when the display content does not change (or often does not change), the central processor of the display system should switch to the low-power mode, the link between the processor and the monitor will be activated as needed. Due to the need to regularly refresh hosts, some of the central processor and memory interfaces also need to be activated, so that the system will not reach the best power budget.

On the other hand, the command mode display architecture allows the monitor to refresh the entire frame buffer directly. However, it is always costly to integrate a full-frame long-frame buffer into a display, especially the high-resolution display that most users need today. This requires the interface chip to have a larger tube core size. The display manufacturer also had to provide a display controller with a specific capacity frame buffer for each display resolution.

For the video mode and command mode display architecture, you usually need to program the display controller registers to set the corresponding display resolution, appearance ratio, and working mode. Mipi does not define any standard protocol to access these internal registers, so different display manufacturers can customize their own command sets.

To avoid conflicts between dedicated display commands of different manufacturers, some manufacturers prefer to enable the display to be initialized by themselves so that the display can work normally without the configuration of the mipi host controller. In this case, a display usually has a PROM memory that stores display parameters. This is very convenient, but the prom also occupies a large storage space.

Main factors for Design Consideration
To achieve optimal system utilization, device manufacturers also need to consider the following factors.

● A High-conversion-efficiency LVS should be integrated inside the monitor, and only one external power supply voltage should be input to the display system.

● For the clock generated through the internal PLL, the external input reference clock is usually required. The frequency of the reference clock ranges from 32 kHz to several MHz. D-PHY is the scalable, low-power, high-speed physical layer standard that will be supported by several MII interface standards. Some D-PHY timing parameters also require a reference clock as a signal reference. In combination with the reference clock usage, the frequency within a dozen MHz is very common. Generally, an internal oscillator will generate a very low frequency clock as a reference clock feedback to the PLL, and generate a display controller by doubling the frequency required by the D-PHY logic.