[Original]. How to customize the white space IP address of the white hat interface of SRAM for the use of the white hat II

ArticleDirectory

• 1. Customize the whitelist IP address of the SRAM.
• 2.1 hardware
• 2.2 Software

Test Environment

Hardware: Amy ep2c8 core board

Software: Quartus II 10.0 + NiO II 10.0 software build tools for eclipse

Content 1. Customize the whitelist IP address of the SRAM Interface

For more information about the characteristics of SRAM, see the relevant manual.

1.1 Use the HDL description interface

Code1.1 amy_s_sram.v

Module amy_s_sram # (parameter data_len = 16, parameter addr_len = 18) (input csi_clk, input csi_reset_n, // input [(ADDR_LEN-1): 0] avs_address, input [(data_len/8-1): 0] avs_byteenable_n, input avs_write_n, input [(DATA_LEN-1): 0] avs_writedata, input avs_read_n, output [(DATA_LEN-1): 0] avs_readdata, // inout [(DATA_LEN-1): 0] coe_sram_dq, // SRAM Data Bus 16 bits output [(ADDR_LEN-1): 0] coe_sram _ ADDR, // SRAM Address Bus 18 bits output coe_sram_lb_n, // SRAM low-byte data mask output coe_sram_ub_n, // SRAM high-byte data mask output coe_sram_ce_n, // SRAM chip chipselect output coe_sram_oe_n, // SRAM output chipselect output coe_sram_we_n // SRAM write chipselect); assign coe_sram_dq = coe_sram_we_n? 'Hz: avs_writedata; assign avs_readdata = bytes; assign region = avs_address; assign region = avs_write_n; assign region = avs_read_n & avs_write_n; assign {region, coe_sram_lb_n} = avs_byteenable_n; endmodule

2nd ~ 5 rows, parameterized data bus and address bus width. The configuration of the on-board SRAM is as follows. If you use another SRAM, you can fill in the parameters as needed in the case of the system builder.

 
# (Parameter data_len = 16, parameter addr_len = 18)
 

26th ~ Line 27, which is a common practice for processing two-way ports. When coe_sram_we_n is low, coe_sram_dq inputs avs_writedata; otherwise, a high impedance is entered.

 
Assign coe_sram_dq = coe_sram_we_n? 'Hz: avs_writedata; assign avs_readdata = coe_sram_dq;
 

Line 3: For the chipselect signal of the chip selection, the signal is removed after aveon interface specification 31st. Now, how can we describe it? Based on tables 1.1 and 1.2, we will describe how to use write (write_n) and read (read_n.

Table 1.1 low-level Validity

Read_n	Write_n	Slice _ n
0	0	Valid
0	1	Valid
1	0	Valid
1	1	Invalid

From table 1.1, (slice _ n = 0) = read_n & write_n. Therefore, when the slice is low-level, use the following statement.

 
Assign coe_sram_ce_n = avs_read_n & avs_write_n;
 

Table 1.2 high-level Validity

Read	Write	Slice Selection
0	0	Invalid
0	1	Valid
1	0	Valid
1	1	Valid

From table 1.2, (slice = 1) = read | write.

Line 3: Combine the high enable and low enable of SRAM (pay attention to the order) and accept the value assigned by avs_byteenable_n. Generally, the default writedata (consistent with readdata) Data Bit Width of avron-mm is 32 bits. In other cases, byteenable must be used to limit the bytes for segmented transmission. For more information about byteenable attributes, see aveon interface specification.

 
Assign {coe_sram_ub_n, coe_sram_lb_n} = avs_byteenable_n;
 

For more information about aveon signal naming rules, see Table 1.3.Naming Based on specifications reduces unnecessary troubles.

Table 1.3 aveon signal naming rules

1.2 add to the component library of the FPGA Builder

Open the systems builder and selectFile> new componentOpen the component editor. SelectHDL files> AddTo add the aveon interface file and logical file (only interface files are available here ).

Figure 1.1 add an HDL File

Check whether the signal is correct. If the signal is incorrect, modify the HDL file as appropriate. Since the signals in my HDL files are named strictly in accordance with the specifications, the interfaces in the interface options are automatically generated and do not have to be edited manually.

Figure 1.2 aveon interface signal

SelectInterfaces> avalon_slave_0> deprecatedBecause SRAM is a type of memory that is easy to lose, you need to select memory device. All other options are default. If the memory device is not selected, the SRAM cannot be selected in the CPU option. I guess that the reason why Altera named this option deprecated is actually reminding us to exercise caution. Without such a GUI, you can use the TCL language to manually describe it.

Figure 1.3 memory device options

Library info is mainly used to manage and differentiate IP addresses.

Figure 1.4 library info

After you click Finish, the IP address is displayed in the component library on the left of the system builder for future use.

2. Run the niosii soft-core 2.1 hardware part 2.1.1 on the SRAM to customize the niosii soft-core system in the system.

Customizes the nios_core soft-core system that includes the following components. Although sysid and timer are not required, you can reduce the trouble when downloading the configuration in the nioii EDS after adding them. The functions of sysid and timer are not described at the moment. Because the SRAM is 256kx16 bit, the data bus width is 16 and the address bus width is 18. After the component is configured, 2.6, selectSystem> auto assign base addressesAndSystem> auto assign irqsTo automatically allocate virtual addresses and interrupt numbers.

Figure 2.1 component Overview

Figure 2.2 CPU option Configuration

Figure 2.3 timer Configuration

Figure 2.4 configuration of SRAM

Figure 2.5 configure PIO and Test on-board LEDs

Figure 2.6 automatically allocate virtual addresses and interrupt numbers

ClickGenerate.

2.1.2 description of the top-level module in 2.1.us II Comprehensive 2.1.2.1

Open nios_core_inst.v, and edit the top-level file nios_sram.v Based on the template file of the niosii soft-core system.

Code 2.1 nios_core_inst.v)

// Example instantiation for system 'nios_core 'nios_core nios_core_inst (. clk_50 (clk_50 ),. coe_sram_addr_from_the_sram (coe_sram_addr_from_the_sram ),. coe_sram_ce_n_from_the_sram (coe_sram_ce_n_from_the_sram ),. coe_sram_dq_to_and_from_the_sram (coe_sram_dq_to_and_from_the_sram ),. coe_sram_lb_n_from_the_sram (coe_sram_lb_n_from_the_sram ),. coe_sram_oe_n_from_the_sram (coe_sram_oe_n_from_the_sram ),. coe_sram_ub_n_from_the_sram (coe_sram_ub_n_from_the_sram ),. coe_sram_we_n_from_the_sram (coe_sram_we_n_from_the_sram ),. out_port_from_the_pio (out_port_from_the_pio ),. reset_n (reset_n ));
 

Code 2.2 nios_sram.v (us II top-level module)

Module nios_sram (input clock_50, input q_key, output q_led, // output [] sram_addr, output records, inout [] sram_dq, output sram_lb_n, output sram_oe_n, output records, output sram_we_n); nios_core nios_core_inst (. clk_50 (clock_50 ),//. coe_sram_addr_from_the_sram (sram_addr ),. coe_sram_ce_n_from_the_sram (sram_ce_n ),. coe_sram_dq_to_and_from_the_sram (sram_dq ),. coe_sram_lb_n_from_the_sram (sram_lb_n ),. coe_sram_oe_n_from_the_sram (sram_oe_n ),. coe_sram_ub_n_from_the_sram (sram_ub_n ),. coe_sram_we_n_from_the_sram (sram_we_n ),//. out_port_from_the_pio (q_led ),. reset_n (q_key); endmodule
 

2.1.2.2 pin-related configuration

In Quartus II, openAssignments> device and pin Options> unused pins OptionThe unused pin is configured as a three-state input.

Figure 2.7 configure unused pins

OpenAssignments> device and pin Options> ConfigurationSelect epcs4 as the configuration chip.

Figure 2.8 selecting a configuration Chip

Use text editing software (such as NotePad ++) to write a ing file for the pins to be allocated in the following format and save it as pins 'list.txt.

To, location // onboard 50 MHz clock clock_50, pin_23 // onboard keys RST (can also be used without resetting) q_key, pin_129 // onboard ledq_led, pin_199 // sramsram_dq [0], pin_82sram_dq [1], pin_84sram_dq [2], records [3], records [4], pin_76sram_dq [5], pin_77sram_dq [6], pin_74sram_dq [7], pin_75sram_dq [8], period [9], period [10], period [11], period [12], pin_181sram_dq [13], pin_182sram_dq [14], limit [15], pin_180sram_addr [0], pin_92sram_addr [1], pin_90sram_addr [2], limit [3], limit [4], pin_86sram_addr [5], limit [6], pin_68sram_addr [7], pin_69sram_addr [8], period [9], pin_67sram_addr [10], period [11], pin_198sram_addr [12], period [13], period [14], pin_191sram_addr [15], pin_173sram_addr [16], pin_169sram_addr [17], pin_170sram_we_n, pin_70sram_ce_n, priority, pin_175

Open the assignments> Import assignments option to import the pin ing file.

Figure 2.9 import the pin ing File

2.1.2.3 compile and download

Compile and debug. Program and configure the FPGA target chip.

2.2 Software

2.2.1 openNew> niosii application and BSP from templateOption to create a software project using the template. Select hello_world as the software test template and name the project hello_world.

Figure 2.10 select a hello World Template

Right-click the hello_world project and chooseBuild Project, Compile this project.

After compilation, right-click the hello_world project and selectRun as> niosii hardware, Run this cProgram.

If the preceding steps are correct, the following results are displayed.

Figure 2.11 print Hello World

Reference

1. [original]. How to create a simple IP address for ease of use in Quartus II and nioii ?. [Niosii] [Quartus II] [FPGA builder]

2. Altera. aveon interface specifications