Precautions for CS8900 Embedded Ethernet PCB design

1. digital and analog signals cannot be mixed for cabling;

2. The signal line cannot be under cs8900a;

3. Chip 3 pairs of analog power supply, ground pair, 4 pairs of digital power supply, ground pair are added 0.1uf capacitor, the connection line is as short as possible; one end is connected to the capacitor, and the other end is connected to the network;

4. Copper is laid on both sides, copper on the Component layer is connected to the ground network, and copper on the welding layer is connected to the power layer;

5. The matching resistance and capacitance of the transmission line and the receiving line should be as close as possible to cs8900a;

6. The input end is connected with a decoupling capacitor, providing a clean enough and accurate + 3.3 V (or 5 V) voltage and ground potential.

7. The 20 m crystal oscillator should be within the range of 1000mil of the chip, with a short line and no guide holes, and should be placed on the component surface;

8. The 4.99k Ω offset resistance should be connected between the res (#93) and avss3 (#94) pins, and the closer the res pin (#93), the better;

9. Try to keep the output transformer close to RJ45;

10. The sending and receiving signal lines are parallel and of an equal length. They should be as short as possible and distributed on the component plane. The receiving signal line should be at least 25 mil wide and the sending line should be at least mil;

11. The two ground wires are parallel and accompanied with transmission lines, and are laid on the ground plane at the bottom of the transmission and receiving lines.

Http://www.pld.com.cn/blog/more.asp? Name = cameral & id = 1640.

Ethernet controller technical reference manual.pdf

P35:Layout considerations for the cs8900a

Http://www.cirrus.com/en/products/pro/detail/P46.html