Programming applications of commonly used serial EEPROM (part 3)

SPI bus
The serial peripheral interface bus is a three-line serial bus developed by Motorola for data transmission using three lines, which are the sck clock pins, SI data input pin and so data output pin. In addition, the CS chip selection pin can be used to select chips on the same bus, SPI bus has been widely used in EEPROM, single chip microcomputer and various devices. The 25xx series chips in commonly used serial EEPROM use the SPI-compatible bus structure and adopt the advanced coms technology, which is small in size and is an ideal low-power non-volatile memory, it is widely used in various household appliances, communication, transportation, or industrial devices. It is usually used to store the configuration data of devices or individuals. The storage capacity of the 25 series EEPROM manufactured by ATMEL ranges from 1 kb to kb. Some other chips also use the SPI bus, such as the commonly used CPU monitoring chips x5043 and x5045 with a 512-byte SPI interface EEPROM, which is commonly used in the MCU system's watchdog circuit, at the same time, it can also provide storage of small data volumes, bringing a lot of convenience to circuit design. This article uses x5045 as an example to describe the SPI Programming Application and some other functions of x5045. X5045 is produced by Xicor. The voltage ranges from 2.7v to 5.5v and from 4.5v to 5.5v. It can be wiped for up to 1 million times, and the maximum clock frequency can reach 3.3 MHz. Figure 1 shows the x5045 PID encapsulated object diagram.

Figure 1

Figure 2

Figure 2 shows the pin definition of x5045. CS/WDI is the chip selection and watchdog reset input. When Cs is high, the So pin changes to a high-impedance state. In this case, other devices can share the SPI bus and the chip is also in sleep state, when Cs is low, the chip is selected and wakes up from the sleep state. You can perform read/write operations. So is the serial data output, which is output from this script when reading the chip. WP is the write protection pin. When WP is low, the chip write protection cannot be performed on the chip, but other functions are not affected. VSS is the power source. Si is a serial data input that receives data and addresses from the Controller. Sck is the serial clock input, reset is the reset output, and VCC is the power supply. There is also a hold pin in the 25 chip, which is used to keep the input pin, while the hold pin of the 25 chip produced by ATMEL is low-level. When this function is not used, the hold pin must remain high. When the chip is in serial transmission, hold is pulled to a low level and further transmission can be paused. The specific method is to lower the hold after the sck is reduced, otherwise, you cannot pause the transfer before the next sck is reduced. to resume the Serial Transfer, you must increase the hold when the sck is low. When the chip is paused, the SI, so, and sck feet are in high resistance state. At any time, as long as the hold is low, the so will be in high resistance state.
Limited by the length of the article, the following content only focuses on the application of the x5045 chip SPI bus to the program of the eeprom unit. There are 6 commands in the x5040 chip, which are compatible with the instructions on the 25 series chip. That is to say, the Instructions on the 25 series chip do not need to be changed. See table 1.

Orders	Command Format	Description
Wren	0000 0110	Write permitted
Wrdi	0000 0100	Write prohibited
Rsdr	0000 0101	Read Status Register
Wrsr	0000 0001	Write Status Register, used to operate the block write protection identifier and the watchdog identifier
Read	0000 a8011	Read data
Write	0000 a8010	Write Data

Note: A8 is used for the 9th-bit data address.

Table 1 Instruction Set

Write permitted and prohibited
The x5045 chip has an internal write enable register. To write data to the chip, you must first use the Wren command to enable in-chip write enable register first, after writing data, you can use the wrdi command to reset the Register to the prohibited state. When the power-on, wrsr command execution, write command execution, and WP is low, the write enable register is reset to the prohibited state. Figure 3 shows the Operation Sequence of the Wren/wrdi command. First, we need to lower the CS, input data, and input the clock signal to the sck. The data is valid on the rising edge of the clock, and at least 30 NS is kept after the clock rises. Data is serialized, so a single bit is sent at the rising edge of each clock cycle. When operating these two commands, so is in the high-impedance state.

Figure 3 Write enable Sequence

Read/write Status Register
The x5045 chip has a status register, which is used to indicate the chip status and settings and can be read/written. The status register value of the chip is 30 h when it is released. For details about each function, see table 2. Indicates whether the chip is busy with write operations. If the WIP value is "1", the write is in progress. If the WIP value is "0", the write is not in progress. During programming, after writing data, you can query the WIP bit. When the WIP is 0, you can perform the next write operation to avoid writing errors. The write enabling status bit of wel, which is a read-only bit. The wel bit status is determined by the Wren and wrdi commands. After wren is successfully executed, wel indicates "1" to allow data writing. After the wrdi command is successfully executed, wel indicates "0" to prohibit Data Writing. During programming, You can first query the wel bit status. For example, if it is 0, you must run Wren before writing. Bl0 and BL1 set the currently protected block address, which is a read/write bit. The relationship between the two bit settings and the block address is shown in Table 3. After the block content is protected, it can only be read, but cannot be written. Different models of 25 series chips have different capacities, and the BL settings have different protection ranges. Wd1, wd0 watchdog setting bits are unique to x5045/43 and can be read/write bits. In 25 series chips, these two bits are reserved bits, and x5045 has the watchdog function, these two bits are used to set the time when the MCU is feeding the dog. Table 4 shows the time when the dog bit is set. The 6th and 7th bits of the Status Register are reserved bits. When reading status registers, after the rsdr command is sent, so is converted from high-impedance state to output data, starting from the high data bit. Write Status Register. After sending the wsdr command, you can send another byte of status data. The Read-Only bit can be "1" or "0 ", they will not be changed by the wsdr command. Figure 5 and figure 6 show the sequence of the read/write Status Register.

7	6	5	4	3	2	1	0
0	0	Wd1	Wd0	BL1	Bl0	Wel	WIP
0	0	Watchdog 1	Watchdog 0	Block protection 1	Block Protection 0	Write enable status bit	Write protection bit

Table 2 State Register Definitions

BL1	Bl0	Protected address range
0	0	Unprotected
0	1	180h-1ffh
1	0	100h-1ffh
1	1	000h-1ffh

Table 3 BL settings

Wd1	Wd0	Dog feeding time
0	0	1.4 seconds
0	1	600 Ms
1	0	200 ms
1	1	Feature disabled (factory settings)

Table 4 watchdog setting bit

Figure 4 read status register sequence

Figure 5 Write status register sequence

Read data
Figure 6 shows the time sequence when reading data. First, we need to reduce the chunked CS chip and add the 9th bits of the address to be read to the 4th bits of the instruction bytes, after sending the command byte, the first eight digits of the address byte are sent. Then, the so will be converted from the high-impedance state to the output data. Each time a byte of data is transferred, the address pointer inside the chip automatically adds 1 to point to the next data address. If there is still a clock pulse, the data will be output, the output is terminated only when the CS pin is high. When the data of the highest bit address is read, the address Pointer Points to 00 H.

Figure 6 Data Reading sequence (click to view the big chart)

Write Data
Before writing data to a chip, the write enable register must be in the Set bit state. Generally, you do not need to query the write enable register state, but directly use the Wren set bit to write the Enable register. After the Wren command is sent, the CS must be increased. Before the CS is increased, the Enable register is not set. In this case, data transmitted to the chip will not be written. After the write enable register is set to a bit, the CS will be reduced, and the 9th bit of the address to be read will be added to the 4th bytes of the instruction bytes, after sending the Instruction byte, it sends the first eight digits of the address byte and then sends the data to be written. The write command can write 16 bytes consecutively, but the address of these 16 bytes must be on the same page. The address of each page starts from [xxxxx0000] and ends at [xxxxx1111. The operation is to continue sending the following data after each address and data is sent. The address pointers in the chip are automatically accumulated. When the last byte in the page is reached, when the clock continues, the internal address pointer returns to the first address on the page and starts accumulating again to overwrite the previously written data. Note that CS cannot be increased during the operation. CS can be increased only after the last bit of the data bytes is transferred. Otherwise, the write operation is incomplete. After writing data or writing Status Register commands, the chip enters a non-volatile write operation, which takes a certain amount of time, up to 10 ms, you can use the read Status Register during this time and check the WIP bit. When the WIP is 1, the write is still in progress, the next read/write operation can be performed only when the WIP bit is 0. Otherwise, the write operation will be incomplete.

Figure 7 Data Writing sequence (click to view the big chart)

In the following example, a password controller experiment is performed on the master node of the host node. With the x5045 watchdog function, the circuit can be reset and restarted automatically after the circuit is disturbed or crashed in special circumstances to keep the circuit working normally. You can use the data read/write function of x5045 to save or change the password. The instance program included in this article demonstrates the reading and writing of the x5045 Status Register and the reading and writing of the storage bit. The function functions can be directly transplanted to other programs. After the circuit is powered on, the red LED is on. When you press the button, the green LED is on. When you press "3, 1, 5, 8,", the password is correct, the red LED is off, and the green LED is on, the relay is turned on and returns to the power-on Status 10 seconds later. If the correct key value is not pressed within 20 seconds after the first key is pressed, the next key value is entered. The program can be easily changed to a program that can easily change the password, or can be added to the program that records the number of work times, and so on, and upgraded to a more practical program. Figure 9 shows an experimental circuit built on a universal board. The eeprom reader circuit and program provided in the previous article also supports 25 series chips and x5043/45 chips, which can be directly used for read/write.

Figure 7 schematic diagram (click to view the large image)

Figure 9 Physical Map