Pulse generator with adjustable PWM duty ratio frequency

Module Xuanpin #
(Parameter n=25)
(Clk,clr,key_in_f,key_in_z,f_out);
Input clk,clr,key_in_f,key_in_z;
Output Reg F_out;
Reg CLK0,CLK1,CLK2,CLK3,CLK4,CLK5,CLK6,CLK7;
Wire key;
Wire key_z;
REG[8:0] Cnter0;
REG[3:0] Cnter1,cnter2,cnter3,cnter4,cnter5,cnter6,cnter7,cnter8;
Debounce Xiaodou_ut
(
. CLK (CLK),
. Rst_n (CLR),
. Key_n (Key_in_f),
. Key_pulse (Key),
. Key_state ()
);
Debounce Xiaodou_uut
(
. CLK (CLK),
. Rst_n (CLR),
. Key_n (Key_in_z),
. Key_pulse (Key_z),
. Key_state ()
);
reg [2:0] cnter9,z;
[Email protected] (Posedge CLK or Negedge CLR)
if (~CLR) cnter9<=0;
else if (cnter9==4) cnter9<=0;
else if (key_z) cnter9<=cnter9+1;

[Email protected] (Posedge CLK or Negedge CLR)
if (~CLR)
cnter0<=0;
else if (cnter0==n-1)
Begin Cnter0<=0;clk0<=1;end
else if (cnter0<= (25* (cnter9+1))) Begin Clk0<=1;cnter0<=cnter0+1;end
Else
Begin cnter0<=cnter0+1;clk0<=0;end//100k





[Email protected] (Posedge clk0 or Negedge CLR)
if (~CLR)
cnter1<=0;
else if (cnter1==9) begin cnter1<=0; Clk1<=1;end
else if (cnter1<= (cnter9+1)) Begin Clk1<=1;cnter1<=cnter1+1;end
ELSE BEGIN cnter1<=cnter1+1;clk1<=0; end//10k

[Email protected] (Posedge clk1 or Negedge CLR)
if (~CLR)
cnter2<=0;
else if (cnter2==9) begin cnter2<=0;clk2<=1; End
else if (cnter2<= (cnter9+1)) Begin Clk2<=1;cnter2<=cnter2+1;end
ELSE BEGIN cnter2<=cnter2+1;clk2<=0;end//1000




[Email protected] (Posedge clk2 or Negedge CLR)
if (~CLR)
cnter3<=0;
else if (cnter3==9) begin cnter3<=0; Clk3<=1;end
else if (cnter3<= (cnter9+1)) Begin Clk3<=1;cnter3<=cnter3+1;end
ELSE BEGIN cnter3<=cnter3+1; Clk3<=0;end//100


/*[email protected] (Posedge CLK2 or Negedge CLR)
if (~CLR) clk3<=0;
else if (cnter3<key_z) clk3<=1;
else clk3<=0;*/



[Email protected] (Posedge clk3 or Negedge CLR)
if (~CLR) cnter4<=0;
else if (cnter4==9) begin cnter4<=0; Clk4<=1;end
else if (cnter4<= (cnter9+1)) Begin clk4<=1; Cnter4<=cnter4+1;end
ELSE begin Cnter4<=cnter4+1;clk4<=0;end//10

/*[email protected] (Posedge CLK3 or Negedge CLR)
if (~CLR) clk4<=0;
else if (cnter4<key_z) clk4<=1;
else clk4<=0;*/


[Email protected] (Posedge CLK or Negedge CLR)
if (~CLR)
cnter5<=0;
else if (cnter5==9) begin cnter5<=0;clk5<=1; End
else if (cnter5<= (cnter9+1)) Begin Clk5<=1;cnter5<=cnter5+1;end
ELSE BEGIN cnter5<=cnter5+1;clk5<=0;end//2500k

/*[email protected] (Posedge CLK or Negedge CLR)
if (~CLR) clk5<=0;
else if (cnter5<key_z) clk5<=1;
else clk5<=0;*/




[Email protected] (Posedge clk5 or Negedge CLR)
if (~CLR)
cnter6<=0;
else if (cnter6==9) begin cnter6<=0; clk6<=1; End
else if (cnter6<= (cnter9+1)) Begin Clk6<=1;cnter6<=cnter6+1;end
ELSE BEGIN cnter6<=cnter6+1;clk6<=0;end//250k

/*[email protected] (Posedge clk5 or Negedge CLR)
if (~CLR) clk6<=0;
else if (cnter6<key_z) clk6<=1;
else clk6<=0;
*/


[Email protected] (Posedge clk6 or Negedge CLR)
if (~CLR)
cnter7<=0;
else if (cnter7==9) begin cnter7<=0;clk7<=1; End
else if (cnter7<= (cnter9+1)) Begin Clk7<=1;cnter7<=cnter7+1;end
ELSE BEGIN cnter7<=cnter7+1; clk7<=0;end//25k



/*[email protected] (Posedge clk6 or Negedge CLR)
if (~CLR) clk7<=0;
else if (cnter7<key_z) clk7<=1;
else clk7<=0;*/


[Email protected] (Posedge CLK or Negedge CLR)
if (~CLR) cnter8<=0;
else if (cnter8==8) cnter8<=0;
else if (key) cnter8<=cnter8+1;

[Email protected] (Cnter8)
Case (Cnter8)
0:f_out=clk0;
1:F_OUT=CLK1;
2:F_OUT=CLK2;
3:F_OUT=CLK3;
4:F_OUT=CLK4;
5:F_OUT=CLK5;
6:f_out=clk6;
7:F_OUT=CLK7;
Endcase
Endmodule




The realization of the non-fixed duty ratio (frequency adjustment, the duty ratio will follow the change)

Module Pulse_gen
(
Input clk_in,
Inputrst_n_in,
Inputkey_menu,
INPUTKEY_UP,
Inputkey_down,
Outputmenu_state,
Outputregpulse_out
);

Debounce for Key_menu
Debounce debounce_menu (. CLK (Clk_in),. Rst_n (Rst_n_in),. Key_n (Key_menu),. Key_state (menu_state));

Debounce for KEY_UP
Debounce debounce_up (. CLK (Clk_in),. Rst_n (Rst_n_in),. Key_n (KEY_UP),. Key_pulse (Up_pulse));

Debounce for Key_down
Debounce Debounce_down (. CLK (Clk_in),. Rst_n (Rst_n_in),. Key_n (Key_down),. Key_pulse (Down_pulse));

Reg[3:0] cycle;
REG[3:0] duty;
Control cycle and duty cycle
Always @ (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) begin
Cycle<=4 ' D8;
Duty<=4 ' D4;
End ELSE begin
if (menu_state) begin//high-level cycle adjustment, low-level duty ratio adjustment
if (Up_pulse && (cycle<4 ' D15)) cycle <= cycle + 4 ' D1;
else if (Down_pulse && (cycle> (duty+4 ' D1)) cycle <= cycle-4 ' D1;
else cycle <= cycle;
End ELSE begin
if (Up_pulse && (cycle> (duty+4 ' D1)) duty <= duty + 4 ' D1;
else if (down_pulse && (duty>4 ' D0)) duty <= duty-4 ' D1;
else duty <= duty;
End
End
End

reg[3:0]cnt;
counter for cycle
Always @ (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) begin
Cnt<=4 ' D0;
End ELSE begin
if (cnt>=cycle) cnt<=4 ' D0;
else CNT <= CNT + 4 ' D1;
End
End

Pulse Generate with duty
Always @ (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) begin
Pulse_out<=1 ' B1;
End ELSE begin
if (cnt<=duty) Pulse_out<=1 ' B1;
else Pulse_out<=1 ' B0;
End
End

Endmodule

Pulse generator with adjustable PWM duty ratio frequency