Quartus II full compilation with critical warning

Critical warning:the Following clock transfers has no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the Derive_clock_uncertainty command.
Critical warning:from Clock (Rise) to Clock (Rise) (Setup and hold
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Compile without notice, the whole project can run on the board. But when doing powerplay, there appeared this critical Warning:,
 
Critical
Warning:the following clock transfers have no clock uncertainty
Assignment. For more accurate results, apply clock uncertainty
Assignments or use the Derive_clock_uncertainty command.
Critical warning:from Altera_reserved_tck (Rise) to Altera_reserved_tck (Rise) (Setup and hold)
Critical warning:from Altera_reserved_tck (Rise) to Altera_reserved_tck (Fall) (Setup and hold)
Critical warning:from Altera_reserved_tck (Fall) to Altera_reserved_tck (Fall) (Setup and hold)
 
Reference to a lot of literature. Altera says it is a timing issue and provides the following workaround:
 
Solution
 
The
ALTERA_RESERVED_TCK PIN is automatically generated for a design that
Uses a JTAG accessible module such as the Signaltap? II Logic Analyzer,
The In-system Memory Content Editor or the Nios? II Debugger.
 
To constrain this JTAG clock, apply a 10-mhz clock constraint to the this pin.
 
For the timequest Timing Analyzer, use the following command:

Create_clock-period "100.000 ns"-name {ALTERA_RESERVED_TCK} {ALTERA_RESERVED_TCK}

For the Quartus? II Classic Timing Analyzer, use the following command:

Set_global_assignment-name fmax_requirement "Ten MHz"-section_id altera_reserved_tck
Set_instance_assignment-name clock_settings altera_reserved_tck-to Altera_reserved_tck

Any
Datapaths crossing into the ALTERA_RESERVED_TCK clock domain from
Another domain can be set as false paths. Similarly any datapaths
Crossing from the ALTERA_RESERVED_TCK domain to another domain can also
be set as false paths.
 
It seems that some people use this method to have effect. But I have no effect. There is another search for a lot. Many times, although the commands used are different, it is agreed that this is not a problem with timing constraints and is related to using JTAG. Finally found a blog: http://blog.sina.com.cn/s/blog_436c7ed30100lu1q.html
 
I admire the spirit of the blogger's "Leaf out", and I like it too much. To tell the truth, the spirit saved a lot of people and hurt the whole country. But this does not affect me again "leaf out":

Set_clock_uncertainty-setup-rise_from altera_reserved_tck-rise_to Altera_reserved_tck 0.150
Set_clock_uncertainty-hold-rise_from altera_reserved_tck-rise_to Altera_reserved_tck 0.150
 
Set_clock_uncertainty-setup-rise_from altera_reserved_tck-fall_to Altera_reserved_tck 0.150
Set_clock_uncertainty-hold-rise_from altera_reserved_tck-fall_to Altera_reserved_tck 0.150
 
Set_clock_uncertainty-setup-fall_from altera_reserved_tck-fall_to Altera_reserved_tck 0.150
Set_clock_uncertainty-hold-fall_from altera_reserved_tck-fall_to Altera_reserved_tck 0.150
 
These words add up, there is no warning. Want to see this article of the cattle, message criticism, tell me where should I find out these things?
"Turn to others, you refer to the next"

Quartus II full compilation with critical warning