Realization of mean filter algorithm based on FPGA

In order to realize the dynamic image filtering algorithm, the serial port sends the image data to the FPGA Development Board, after the FPGA carries on the image processing algorithm, the dynamic display to the VGA display, the front we have already built the hardware platform to complete, Later, we will use this hardware base platform to implement a series of FPGA-based image processing base algorithm.

Salt and pepper noise (salt & pepper noise) is a common noise in digital images, the so-called salt and pepper, the pepper is black, is white, salty noise is the random appearance of black and white pixels on the image. Salt and pepper noise is a noise caused by the intensity of signal pulses, and the algorithm for generating clear noise is relatively simple.

The mean filter method stores the data as a 3x3 matrix, and then the matrix is obtained. A template is given to the target pixel on the image, which includes the neighboring pixels around it (8 pixels around the center of the target pixel to form a filter template that removes the target pixel itself) and replaces the original pixel value with the average of the entire pixel in the template.

Mean Value Filter

, we want to make the mean filter first to generate a 3x3 matrix. The algorithm operation window usually uses the neighborhood of odd points to calculate the median value, and the most commonly used windows are 3x3 and 5x5 models. The Verilog implementation of the 3x3 window is described below.

(1) through 2 or 3 RAM storage to achieve the 3x3 pixel window;

(2) through 2 or 3 FIFO storage to achieve the 3x3 pixel window;

(3) through 2 rows or 3 rows of shift_ram storage to achieve the 3x3 pixel window;

To achieve mean filtering and median filtering, you must be a 3x3 array, in Altera series, you can use quatusii call IP Core--shift_ram, set parameters.

As shown, where Shiftin is the real-time input data, taps1x,taps2x input data of the 23rd line, when the data input into a row of three, automatically jump to the next line, the final formation of each row is a matrix of three columns, using mean filtering and median filter processing method can be, This basically is each target can find their own corresponding to a 3x3 matrix, the final processing. First into the IP core is the first data, so in the read out of the time is to be placed in line.

Xilinx Vivado also has its own Shift_ram IP core, but only one row of data is cached here, and we need two Shift_ram IP cores and a row of data being entered together to form 3 rows of data. This calls two Shift_ram IP cores to link the two IP levels together.

This system is mainly used by calling two Shift_register IP cores to generate a 3x3 matrix implementation 3x3 Pixel window. The Shift_register IP core defines the width of the data, the number of rows shifted, and the depth of each row. Here we need 8bit. 640 data per line, colleague Shift storage 2 rows. Also select the clock enable Port Clken.

Pixel Data Shift Storage

We set the row to 12 here, so it is obvious that when the data is cached to a single row, it is shifted to the next row, and a 3x3 matrix is generated after two rows are cached.

Cached data

Comparing the data in the first row of the cache to the first row in the 3x3 matrix, the result is the same, apparently correct. The result of the resulting 3x3 matrix is clearly correct.

Total value

Ask for the mean value

We use a two-stage pipeline to consume 2 clock cycles when we calculate the mean, so the data cache that is lost to the write RAM enable can delay two clock cycles! Learn a new time-lapse notation.

To sum the eight points around the center pixel of the 3x3 matrix, we still take the pipeline design method to increase the throughput, and then the mean to replace the value of the target pixel, here the reader can think about how to design, from the waveform view, the results of the calculation is clearly correct. This completes the simulation of the mean filter.

Let's take a look at the board level test video: Http://t.cn/RCJxiGF

Finally, we compare the display effect, for the gray image, the image after the mean filter, you can see that the filtered image has some ambiguity, this is because the mean filter is to make the image smooth processing, pixels high pixel value will be pulled low, the pixel value of low pixels will be pulled high, tend to an average, so the image will be blurred some. And careful people can enlarge the picture will see, the picture will have a few white black spots, which is actually the salt and pepper noise, we also said at the beginning of the article, Salt and pepper noise (salt & pepper noise) is a common noise in digital images, the so-called salt and pepper, pepper is black, is white, Salt and pepper noise is the random appearance of black and white pixels on the image. Mean filter is equivalent to low-pass filtering, there is a tendency to blur the image, the basic inability to salt and pepper noise, so the picture will leave some black and white points. Next I will release the median filter processing based on FPGA, and compare the merits and demerits of the two filtering methods, finally choose a better filtering method for image edge detection and processing.

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Realization of mean filter algorithm based on FPGA