STM32F4 Learning note 10--RTC real time clock

RTC Real-Time Clock
The real-time clock (RTC) is a standalone BCD Timer/counter. RTC provides a calendar clock, two programmable alarm interrupts, and a periodic programmable wake-up flag with interrupt capability. The RTC also includes an automatic wake-up unit for managing low-power modes.
Two 32-bit registers contain seconds, minutes, hours (12 or 24-hour) of binary decimal format (BCD), Day of the week, date, month, and year. In addition, the sub-second value in binary format can be provided.
The system can automatically compensate the days of the month to 28, 29 (leap years), 30, and 31 days. It also allows for daylight saving time compensation.
Other 32-bit registers also contain programmable alarm clocks sub-second, seconds, minutes, hours, days of the week, and dates.
In addition, the accuracy of the crystal oscillator can be compensated by using the digital calibration function.
After power-on reset, all RTC registers are protected against possible non-normal write access.
Regardless of the device status (operating mode, low power mode, or in the Reset state), RTC does not stop working as long as the supply voltage remains within the operating range.

RTC Key Features
A calendar that contains sub-seconds, seconds, minutes, hours (12/24-hour), Day of the week, date, month, and year.
Software programmable daylight saving time compensation.
Two programmable alarms with interrupt function. Alarms can be driven by the combination of any calendar field.
Automatic wake-up unit, which periodically generates a flag to trigger an automatic wake-up interrupt.
Reference Clock Detection: You can use a more accurate second clock source (either Hz or Hz) to improve the accuracy of your calendar.
The sub-second shift feature enables precise synchronization with the external clock.
Shielded Interrupts/events:
-Alarm Clock A
-Alarm Clock B
-Wake-up interrupt
-Time stamp
-Intrusion detection
Digital calibration Circuit (periodic counter adjustment)
-Accuracy of 5 ppm
-Accuracy of 0.95 ppm, obtained in a few seconds of calibration window
Timestamp function for event saving (one event)
Intrusion detection:
-2 intrusion events with configurable filters and internal pull-up
20 Backup registers (80 bytes). When an intrusion detection event occurs, the backup register is reset.
Multiplexing function output (rtc_out), you can select one of the following two outputs:
-rtc_calib:512 Hz or 1 Hz clock output (LSE frequency is 32.768 kHz).
This output can be enabled by adding the coe[23] position in the RTC_CR register. The output can be connected to the device RTC_AF1 function.
-rtc_alarm (Alarm A, alarm B, or wake).
This output can be selected by configuring the osel[1:0] bit of the RTC_CR register. The output can be connected to the device RTC_AF1 function.
RTC multiplexing Function Input:
-RTC_TS: Timestamp event detection. The input can be connected to the device RTC_AF1 and RTC_AF2 functions.
-rtc_tamp1:tamper1 event Detection. The input can be connected to the device RTC_AF1 and RTC_AF2 functions.
-rtc_tamp2:tamper2 event Detection.
-rtc_refin: Reference clock input (usually mains, Hz or Hz).

For stm32f4xx devices, the RTC_AF1 and rtc_af2 multiplexing functions are connected to PC13 and PI8, respectively.

RTC Feature Description
Clock and Prescaler
RTC Clock Source RTCCLK through the clock controller LSE clock, LSI oscillator clock first level HSE clock of the three selected. The programmable Prescaler stage can generate a 1Hz clock for updating the calendar. For maximum price low power, the Prescaler is divided into two programmable prescaler:
· A 7-bit asynchronous divider configured via the prediv_a bit of the Rtc_prer register.
· A 15-bit synchronous prescaler configured via the prediv_s bit of the Rtc_prer register.
To minimize power dissipation, it is recommended to configure the asynchronous Prescaler to a higher value.
To use an LSE with a frequency of 32.768 kHz to obtain an internal clock (ck_spre) of 1 Hz, the asynchronous Prescaler factor must be set to 128 and the synchronous Prescaler factor set to 256.
The minimum value of the crossover factor is 1 and the maximum value is 2^22.
This corresponds to a maximum input frequency of approximately 4 MHz.
Fck_apre can be obtained according to the following formula:

The Ck_apre clock is used to provide a clock for the binary RTC_SSR sub-second decrement counter. When the counter is counted to 0 o'clock, the contents of the prediv_s are overloaded with RTC_SSR.
Fck_spre can be obtained according to the following formula:

The Ck_spre clock can be used either to update the calendar or as a time base for 16-bit wake-up auto reload timers. For a shorter timeout period, the 16-bit wake-up auto-reload timer can also be run with the rtcclk of the programmable 4-bit asynchronous Prescaler.

The

Live clock and calendar
RTC calendar time and date registers can be accessed through the shadow registers that are synchronized with the PCLK1 (APB1 clock). These time and date registers can also be accessed directly, which avoids the duration of waiting for synchronization.
RTC_SSR corresponds to sub-second
Rtc_tr corresponds to the time
Rtc_dr corresponds to the date
every two rtcclk cycles, the current calendar value is copied to the shadow register, and RTC_ISR position of the RSF register is 1. The copy operation is not performed in shutdown and Standby mode. When you exit both modes, the shadow register is updated after a maximum of 2 rtcclk cycles.
when the app reads the calendar register, it accesses the contents of the Shadow register. You can also access the calendar register directly by using the Bypshad control location of the RTC_CR register. By default, the bit is zeroed and the user accesses the shadow register.
When reading the RTC_SSR, RTC_TR, or RTC_DR registers in bypshad=0 mode, the APB clock frequency (FAPB) must be at least 7 times times the RTC Clock frequency (FRTCCLK). The
Shadow register is reset by the system reset.

The

Programmable Alarms
RTC Unit provides two programmable alarms, alarm A and alarm B. The
can be programmed by the Alrae and Alrbe positions in the RTC_CR register to enable programmable alarm functions. If the calendar sub-second, second, minute, hour, date, or day match the values programmed in the alarm register Rtc_alrmassr/rtc_alrmar and RTC_ALRMBSSR/RTC_ALRMBR, the ALRAF and ALRBF flags are set to 1. Each calendar field can be selected individually through the mskx bits of the Rtc_alrmar and RTC_ALRMBR registers, as well as the RTC_ALRMBSSR bits of the RTC_ALRMASSR and MASKSSX registers. The alarm clock can be interrupted by the Alraie and Alrbie bits in the RTC_CR register.
Alarm A and alarm B (if enabled by the bit osel[0:1 in the RTC_CR register) can be connected to the Rtc_alarm output. The Rtc_alarm polarity can be configured by the POL bit of the RTC_CR register.
Note: If you select the second field (MSK0 bit reset in Rtc_alrmar or RTC_ALRMBR), the synchronization prescaler set in the Rtc_prer
Register must be at least 3 to ensure that the alarm is running correctly.

Periodic automatic wake-up
The periodic wake-up flag is generated by a 16-bit programmable automatic reload decrement counter. The wake-up timer range can be extended to 17 bits.
This wake-up function can be enabled through the Wute bit in the RTC_CR register.
The clock input for the wake-up timer can be:
RTC Clock (RTCCLK) of 2, 4, 8, or 16.
When the RTCCLK is LSE (32.768 kHz), the configurable wake-up interrupt period is between 122μs and + S, and the resolution is as low as 61μs.
Ck_spre (typically 1 Hz internal clock)
When the Ck_spre frequency is 1 Hz, the wake-up time is about 1s to 36h and the resolution is 1 seconds. This larger programmable time range is divided into two parts:
-wucksel [2:1] = 10 o'clock 1s to 18h.
-wucksel [2:1] = 11 o'clock is about 18h to 36h. In the latter case, 216 is added to the current value of the 16-bit counter. After the initialization sequence is complete (see programmed wake-up timer on page No. 577), the timer starts to decrement the count. The decrement count remains in effect when the wake-up function is enabled in low-power mode. Additionally, when the counter is counted to 0 o'clock, the WUTF flag of the RTC_ISR register is set to 1, and the wake register uses its overloaded value (Rtc_wutr register value) to reload. You must then use the software to clear the 0 Wutf logo.
It causes the device to exit the low-power mode by making the Wutie position in the RTC_CR2 register a periodic wake-up interrupt.
The flag can be connected to the Rtc_alarm output if it has been enabled to periodically wake the flag through bit osel[0:1 in the RTC_CR register. The Rtc_alarm polarity can be configured by the POL bit of the RTC_CR register.
System resets and low power modes (sleep, shutdown, and standby) have no effect on the wake-up timer.

RTC Initialization and Configuration
RTC Register Access
The RTC register is a 32-bit register. In addition to read access to the Calendar Shadow register when bypshad=0, the APB interface introduces 2 wait cycles when accessing the RTC register.
RTC Register Write protection
After the system is reset, the RTC register can be protected by the DBP bit of the PWR Power Control Register (PWR_CR) to prevent abnormal write access. The DBP position must be 1 to enable write access to the RTC register.
All RTC registers are write-protected after power-on reset. Write to the RTC register by writing a key to the Write protection register (RTC_WPR).
To unlock write protection for all RTC registers (except Rtc_isr[13:8], RTC_TAFCR, and RTC_BKPXR), you need to perform the following steps:
1. Write "0xCA" to the RTC_WPR register.
2. Write "0x53" to the RTC_WPR register.
Writing an incorrect keyword will activate write protection again.
The protection mechanism is not affected by the system reset.
Reset RTC
Some bits of the Calendar shadow Register (RTC_SSR, RTC_TR, and RTC_DR) and the RTC Status register (RTC_ISR) are reset to their default values through all available system reset sources.
Instead, the following registers are reset to their default values by a power-on reset and are not affected by the system Reset: RTC Current Calendar Register, RTC Control Register (RTC_CR), Prescaler Register (rtc_prer), RTC Calibration Register (RTC_CALIBR or RTC_ CALR), RTC Shift Register (RTC_SHIFTR), RTC Timestamp Register (RTC_TSSSR, RTC_TSTR, and RTC_TSDR), RTC Intrusion and Multiplexing feature configuration register (RTC_TAFCR), RTC Backup Register (RTC_ BKPXR), wake-Up Timer register (RTC_WUTR), and alarm A and alarm B registers (Rtc_alrmassr/rtc_alrmar and rtc_alrmbssr/
RTC_ALRMBR).
In addition, if the reset source is not a power-on reset source, the RTC will continue to work when a system reset occurs. When a power-on reset occurs, RTC stops working, and all RTC registers are set to their respective reset values.
RTC Sync
RTC can be synchronized with high-precision remote clocks. After reading the sub-second field (RTC_SSR or RTC_TSSSR), you can calculate the precise deviation between the time of the remote clock and the RTC. After that, you can use RTC_SHIFTR to "Pan" the RTC's clock for fraction seconds, which can be adjusted to eliminate this bias.
The RTC_SSR contains the value of the synchronous Prescaler counter. This allows you to calculate the exact time of the RTC with a resolution as low as 1/(prediv_s + 1) seconds. Therefore, the resolution can be increased by increasing the value of the synchronous Prescaler (prediv_s[14:0]). When prediv_s is set to 0x7FFF, the maximum allowable resolution (30.52μs, 32768 Hz) can be obtained.
However, increasing the prediv_s means that the prediv_a must be lowered to maintain the output of the synchronous Prescaler at 1 Hz. In this way, the output frequency of the asynchronous prescaler increases, and the dynamic power consumption of the RTC increases correspondingly.
RTC can be fine-tuned using the RTC Translation Control Register (RTC_SHIFTR). You can use a size of 1/
The resolution of (prediv_s + 1) seconds writes to the RTC_SHIFTR, translating the clock (delay or advance) up to 1 seconds. In this panning operation, the subfs[14:0] value is added to the synchronous Prescaler counter ss[15:0]: This causes the clock to delay. If the add1s position is 1 at the same time, it will increase by one second, while the time minus is fraction seconds, so the clock will advance.
Note: Before initializing the pan operation, the user must check the confirmation ss[15] = 0 To ensure that no overflow occurs.
When a write operation is performed on the RTC_SHIFTR register to initiate a panning operation, the hardware resets the SHPF flag by 1 to indicate that the panning operation is pending. When the panning operation is complete, the hardware will clear the bit.
Note: This synchronization function is incompatible with the reference clock detection function: When refckon=1, the firmware cannot
The line write operation.
Error statusrtc_deinit (void) function: Redefine RTC Register to their reset value, this function cannot reset RTC clock Source and RTC backup data register.
ErrorStatus rtc_init (rtc_inittypedef*rtc_initstruct) function: Based on the RTC parameter configuration RTC example, the RTC Divider Register is write-protected and can only be written in initialization mode.
void Rtc_structinit (rtc_inittypedef*rtc_initstruct) function: Initializes all RTC_INITSTRUCT members to a reset value.
void Rtc_writeprotectioncmd (Functionalstate newstate) feature: Enable or prohibit write protection. All RTC registers are write-protected except for (RTC_ISR[13:8],RTC_TAFCR,RTC_BKBXR). The secret key to write the error will be newly activated write protection, the write protection mechanism does not accept the system reset effect.
Errorstatue Rtc_enterinitmode (viod) function: Into the RTC initialization mode, the RTC initialization mode is write-protected mode, before calling this function to call the function Rtc_writeprotectioncmd (DISABLE) first.
void Rtc_exitinitmode (void) function: Exits the RTC initialization mode, and after the initialization sequence is complete, the calendar does not start working after the 4 rtcclk clocks. The RTC initialization mode is write-protected, calling the function Rtc_writeprotectioncmd (DISABLE) before calling the function.
ErrorStatus rtc_waitforsynchro (void) function: Wait until the RTC time and date register are synchronized with the APB clock. RTC Synchronization • The mode is write-protected, and the function Rtc_writeprotectioncmd (DISABLE) is called before use.
ErrorStatus rtc_refclockcmd (functionalstate newstate) enables or disables the RTC reference clock.

Time and date initialization and configuration
To program the initial time and date calendar values, including the time format and Prescaler configuration, you need to do this in the following order:
1. Place the init position in the RTC_ISR Register 1 to enter initialization mode. In this mode, the calendar counter stops working and its value is updatable.
2. Poll the INITF bit in the RTC_ISR register. When INITF 1 o'clock enters the initialization stage mode. Approximately 2 RTCCLK clock cycles are required (due to clock synchronization).
3. To generate a 1 Hz clock for the calendar counter, you should first program the synchronous Prescaler factor in the Rtc_prer register and then program the asynchronous Prescaler factor. Even if you only need to change one of these two fields, you must perform two separate write accesses to the Rtc_prer register.
4. Load the initial time and date values in the shadow register (RTC_TR and RTC_DR), and then configure the time format (12 or 24-hour system) with the FMT bit in the RTC_CR register.
5. Exit initialization mode by clearing 0 INIT bits. The actual calendar counter value is then automatically loaded, and the count restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.
Note: After a system reset, the app can read the INITS flag in the RTC_ISR register to check whether the calendar has been initialized. If the flag is 0, the calendar has not been initialized because the year field is set to its default value (0x00) when the power-on reset occurs.
To read the calendar after initialization, you must first check with the software that the RTC_ISR Register's RSF flag is set to 1.
ErrorStatus rtc_settime (uint32_trtc_format,rtc_timetypedef*rtc_timestruct) function: Set the current RTC time
void Rtc_timestructinit (rtc_timetypedef*rtc_timestruct) function: Initializes rtc_timestruct struct member to reset value
void Rtc_gettime (uint32_t rtc_format,rtc_timetypedef*rtc_timestruct) function gets RTC time.
uint_32t rtc_getsubsecond (void) function: Get sub-second
ErrorStatus rtc_setdate (uint32_t rtc_format,rtc_datetypedef*rtc_datestruct)
void Rtc_datestructinit (Rtc_datetypedef*rtc_datestruct)
void Rtc_getdate (uint32_t rtc_format,rtc_datetypedef*rtc_datestruct) These functions are set to date, function is the same as the function of setting time.

Programming alarm
to program or update a programmable alarm clock (alarm A or alarm b), you must perform a similar procedure:
1. Alrae or Alrbe bits in the RTC_CR register are cleared 0 to prevent alarm A or alarm B.
2. Poll the ALRAWF or ALRBWF bit in the RTC_ISR register until one of the 1 is set to make sure the alarm register is accessible. Approximately 2 RTCCLK clock cycles are required (due to clock synchronization).
3. Programmed Alarm A or alarm B register (Rtc_alrmassr/rtc_alrmar or RTC_ALRMBSSR/RTC_ALRMBR).
4. Place the Alrae or Alrbe position 1 in the RTC_CR register to enable alarm A or alarm B again.
Note: After approximately 2 rtcclk clock cycles (due to clock synchronization), changes to the RTC_CR register are performed.
void Rtc_setalarm (uint32_t rtc_format, uint32_t rtc_alarm, rtc_alarmtypedef*rtc_alarmstruct) function: RTC Alarm time configuration. The
Void Rtc_alarmstructinit (rtc_alarmtypedef*rtc_alarmstruct) function initializes the struct member of the RTC_ALARMTYPEDEF type to the reset value.
void Rtc_getalarm (uint32_t rtc_format, uint32_t rtc_alarm, rtc_alarmtypedef*rtc_alarmstruct) function: Gets the RTC alarm value.
ErrorStatus rtc_alarmcmd (uint32_t rtc_alarm,functionalstate newstate) Feature: Disables or enables RTC alarms.
void Rtc_alarmsubsecondconfig (uint32_t rtc_alarm,uint32_t rtc_alarmsubsecondvalue,uint32_t RTC_ Alarmsubsecondmask) feature configures the RTC alarma/b Sub-second
Rtc_getalarmsubsecond (uint32_t rtc_alarm) function: The sub-second time of the RTC.

Programmable Wake-Up timer
To configure or change the automatic reload value of the wake-up timer (wut[15:0 in RTC_WUTR), you need to follow these steps:
1. Clear 0 RTC_CR in Wute to disable wake-up timer.
2. Poll the WUTWF in RTC_ISR until the location 1 to ensure that the wake-up auto reload timer and wucksel[2:0] bit are accessible. Approximately 2 RTCCLK clock cycles are required (due to clock synchronization).
3. Program wake-up automatically reload value wut[15:0] and select wake-Up clock (wucksel[2:0] bit in RTC_CR). The wute position in the RTC_CR register will be 1 to enable the timer again. The wake-up timer restarts the decrement count.

void Rtc_wakeupclockconfig (uint32_t rtc_wakeupclock) feature: Configuring the RTC wake-up clock source
void Rtc_setwakeupcounter (uint32_t rtc_wakeupcounter) function: Configure the RTC Wake Count to ensure that RTC wake is disabled before using this function Rtc_wakeupcmd (DISABLE)
uint32_t rtc_getwakeupcounter (void) function: Gets the count value of the wake-up timer
ErrorStatus rtc_wakeupcmd (functionalstate newstate) function: Enable or disable wake-up timer

Time stamp function
The TSE position of the RTC_CR register is 1 to enable time stamping.
When a timestamp event is detected on the pin to which the TIMESTAMP standby function is mapped, the calendar is saved to the timestamp register (RTC_TSSSR, RTC_TSTR, and RTC_TSDR). When a timestamp event occurs, the timestamp flag bit (TSF) in the RTC_ISR register is set to 1.
By using the Tsie position in the RTC_CR Register 1, an interrupt can be generated when a timestamp event occurs.
If a new timestamp event is detected under a time stamp flag (TSF) that has 1, the timestamp overflow flag (TSOVF) will be set to 1, and the timestamp register (RTC_TSTR and RTC_TSDR) will persist the result of the previous event.
Note: Because of the synchronization process, TSF will set 1 for 2 Ck_apre cycles after a timestamp event.
There is no delay in placing the tsovf 1 o'clock. This means that if two timestamp events occur in succession, the tsovf may be "1" and the TSF remains "0". Therefore, it is recommended to poll the TSOVF only after the TSF is detected as "1".
Note: If a timestamp event occurs immediately after the TSF bit clear 0, both the TSF and TSOVF bits will be set to 1. To prevent the event from being masked while a timestamp event occurs, the application must not write "0" to the TSF bit unless the TSF bit has been read as "1".
Additionally, intrusion events can cause timestamps to be logged. For a description of the tampts control bit, see section 23.6.17: RTC intrusion and Multiplexing feature configuration register (RTC_TAFCR). If the timestamp event uses the same pin as an intrusion event configured to filter mode (Tampflt is set to a value other than 0), the timestamp mode of the intrusion detection event must be selected by placing the Tampts "1" in the RTC_TAFCR register.
Time Stamp multiplexing function
The timestamp multiplexing feature (RTC_TS) can be mapped to RTC_AF1 or rtc_af2, depending on the value of the Tsinsel bit in the RTC_TAFCR register (see section 23.6.17: RTC intrusion and Multiplexing feature configuration register (RTC_TAFCR)). If RTC_AF1 is used as a filtering mode TAMPER (Tampflt is set to a value other than 0), timestamp events are not allowed to be mapped to rtc_af2.
void Rtc_timestampcmd (uint32_t rtc_timestampedge,functionalstate newstate) Feature: Enables or disables the time stamp of the RTC.
void Rtc_gettimestamp (uint32_t rtc_format,rtc_timetypedef*rtc_stamptimestruct,rtc_datetypedef**rtc_ stampdatestruct) Function: The value of the time stamp is never met.
unit32_t rtc_gettimestampsubsecond (void) function: The sub-second time to get the timestamp.

Intrusion detection
There are two intrusion detection inputs available. Both inputs can be configured for edge detection and can also be configured for level detection with filtering.
RTC Backup Register
The Backup register (RTC_BKPXR) includes 20 32-bit registers for storing 80 bytes of user application data. These registers are implemented in the backup domain and can be powered up via the VBAT when the VDD power is off. The backup register will not be reset at System reset or power reset, nor will it be reset when the device wakes from standby mode.
When an intrusion detection event occurs, the backup register is reset.
Intrusion detection Initialization
Two intrusion detection inputs are associated with the flag tamp1f/tamp2f in the RTC_ISR2 register, respectively. Each input can be enabled by the corresponding tamp1e/tamp2e position in the RTC_TAFCR register.
The intrusion detection event resets all backup registers (RTC_BKPXR).
By using the Tampie position in the RTC_TAFCR Register 1, an interrupt can be generated when an intrusion detection event occurs.
Time stamp of the intrusion event
When tampts "1", any intrusion event can cause a timestamp event to occur. In this case, as with normal timestamp events, the TSF bit or tsovf bit in RTC_ISR is set to 1. At the same time as TSF or TSOVF 1, the affected intrusion flag registers (tamp1f, tamp2f) will also be placed with 1.
Edge Detection for intrusion input
If the Tampflt bit is "00", the TAMPER pin generates an intrusion detection event (Rtc_tamp[2:1]) when the rising or falling edge is observed (according to the corresponding TAMPXTRG bit). When Edge detection is selected, the internal pull-up resistor on the intrusion input is suppressed.
Note: To avoid loss of intrusion detection events, signals used for edge detection and TAMPXE use logic and operations to detect intrusion events,
To avoid losing the intrusion event that occurs before the Enable Tamperx pin.
When TAMPXTRG = 0 o'clock: If the Tamperx multiplexing function has become high before enabling intrusion detection
(tampxe position 1), the intrusion event is detected immediately after Tamperx, even if the TAMPXE
The Tamperx pin does not appear on the rising edge after 1.
When TAMPXTRG = 1 o'clock: If the Tamperx multiplexing function has become low before enabling intrusion detection,
The intrusion event can be detected immediately after the Tamperx is enabled (even after the TAMPXE 1 Tamperx
No falling edge on the foot).
After detecting an intrusion event and clearing 0, you should disable the Tamperx Multiplexing feature before re-programming the backup register (RTC_BKPXR), and then re-enable (Tampxe 1). This prevents the application from writing to the backup register when the Tamperx value still indicates intrusion detection. This is equivalent to the level detection of the Tamperx multiplexing function.
Note: Intrusion detection is still valid when the VDD power is turned off. To avoid accidentally resetting the backup register, the PIN to which the TAMPER multiplexing function is mapped should be externally connected to the correct level.
Detection of intrusion input with filter level
Level detection with filtering is performed by setting the Tampflt to a value other than 0. In the TAMPXTRG bit (tamp1trg/
TAMP2TRG) generates an intrusion detection event when a specified level continuously occurs with 2, 4, or 8 (depending on the Tampflt value) sampled.
These inputs are pre-charged via the I/O internal pull-up resistor until the state of the intrusion input is sampled, unless the intrusion input is tamppudis by 1. The duration of the pre-charge is determined by the tampprch bit, allowing to increase the capacitance on the intrusion input.
The tampfreq can be used to determine the sampling frequency for level detection so that the intrusion detection delay is optimally balanced against the pull-up resistor power dissipation.
Note: For the electrical characteristics of the pull-up resistor, refer to the data sheet.
void Rtc_tampertriggerconfig (uint32_t rtc_tamper,uint32_t rtc_tampertrigger) function: Trigger mode of Tamper pin
void Rtc_tampercmd (uint32_t rtc_tamper,functionalstate newstate) function: Enable or disable intrusion detection
void Rtc_tamperfilterconfig (uint32_t tamperfilter)
void Rtc_tampersamplingfreqconfig (uint32_t rtc_tampersamplingfreq)
void Rtc_tamperpinsprechargeduration (uint32_t rtc_tamperprechargeduration)
void Rtc_timestampontamperdetectioncmd (Functionalstate newstate)
void Rtc_tamperpullupcmd (Functionalstate newstate)
void Rtc_writebackupregister (uint32_t rtc_bkp_dr, uint32_t data) function: Write data to RTC backup data register
uint32_t rtc_readbackupregister (uint32_t rtc_bkp_dr) function: Reads data from the backup data register.
void Rtc_tamperpinselection (uint32_t rtc_tamperpin) function: Select the RTC tamper pin.
void Rtc_timestamppinselection (uint32_t rtc_timestamppin) function: Select RTC timestamp pin

RTC Interrupt
All RTC interrupts are connected to the Exti controller.
To enable RTC alarms to be interrupted, you need to do this in the following order:
1. Configure the Exti line 17 to break mode and enable it, then select the rising edge to be active.
2. Configure the Rtc_alarm IRQ channel in the NVIC and make it available.
3. Configure RTC to generate RTC alarm (alarm A or alarm B).
To enable RTC wake-up interrupts, you need to do this in the following order:
1. Configure the Exti line 22 to break mode and enable it, then select the rising edge to be active.
2. Configure the Rtc_wkup IRQ channel in the NVIC and make it available.
3. Configure RTC to generate RTC Wake-up Timer events.
In order for RTC intrusion to be interrupted, the following sequence of operations is required:
1. Configure the Exti line 21 to break mode and enable it, then select the rising edge to be active.
2. Configure the Tamp_stamp IRQ channel in the NVIC and make it available.
3. Configure RTC to detect RTC intrusion events.
In order to enable the RTC timestamp to be interrupted, the following sequence is required:
1. Configure the Exti line 21 to break mode and enable it, then select the rising edge to be active.
2. Configure the Tamp_stamp IRQ channel in the NVIC and make it available.
3. Configure RTC to detect RTC Timestamp events.

void Rtc_itconfig (uint32_t rtc_it,functionalstate newstate) function: Enable or disable RTC interrupt
FlagStatus rtc_getflagstatus (unit32_t rtc_flag) function: Query RTC flag, mainly used for non-interrupt function
void Rtc_clearflag (uint32_t rtc_flag) function: Clear RTC flag, mainly for non-disruptive functions
Itstatus rtc_getitstatus (uint32_t rtc_it) function: Query RTC interrupt flag, mainly used for interrupt function
void Rtc_clearitpendingbit (uin32_t rtc_it) function: Clears the RTC interrupt flag, primarily for interrupt functions
Static uint8_t rtc_bytetobcd2 (uint8_t Value) function: For BCD and binary number of the mutual turn
Static uint8_t Rtc_bcd2tobyte (uint8_t Value) function: For BCD and binary number of the mutual turn

RTC Low Power Mode

STM32F4 Learning note 10--RTC real time clock