SVA description (i)

SystemVerilog Assertion (SVA): is a descriptive language that can easily describe timing-related situations, so it is primarily used in protocol checks and protocol overrides. SVA in the SystemVerilog emulator

Dispatch interval after RTL, before Testbench. So the same 1: assertion can only be sampled to the RTL value of the previous moment. Because it is a descriptive statement, ";" Use more.

When the assertion fails, the information is automatically printed to the log file, and the user can customize the print content.

Assertion Name:assert xxxx;

$display ("xxxxx");

Else

$display ("xxxxx");

SVA is divided into concurrent assertions: clock-based, scheduling interval according to assertion, can be in the process block (always initial), modules (module), Interface (interface), programs (program) defined.

Instant Assertion: An event-based, essentially not a time-series relationship, is evaluated immediately. For inspection. can only be defined in the procedure block (always initial).

Another difference is that concurrent assertions are declared with property, and instant assertions are not required.

Always

Begin

A_ia:assert (a && b); Instant assertion

End

Because concurrent assertions apply more, they are all in the same concurrency assertion:

Concurrent assertions can customize a SVA block to describe the timing of their own requirements, two keywords: sequence, property.

Sequence S1; Sequence allows you to define a smaller clock description

A # #2 B;

Endsequence

Property S2; Property an assert can have only one

@ (Posedg clk) s1;

EndProperty

S3:assert Property (S2); Standard Form Name:assert property ();

A function embedded in an assertion that represents the rising and falling edges of a signal: $rose (expression or signal) $fell (expression or signal) $stable (expression or signal)

Sequence S2;

@ (Posedge CLK) $rose (a); The rising edge of the clock is still used Posedge, and the rising edge of the signal is only used $rose ();

Endsequence

Description of timing delay in assertion: # #表示延时, but pay attention to triggering add. ended, otherwise the SVA default is aligned at the start time, that is, if the assertion 3 time is triggered, and the 5 moment succeed, but the assertion

It will also cover 3 moments of right and wrong.

Sequence S2;

@ (Posedge CLK) a # #2 B; A is a high level delay after 2 clocks if B is high, the assertion succeeds.

Endsequence

Property p12;

@ (Posedge CLK) (a && B) |-> ##[1:3] C; Equivalent (a && b) |-> # #1 C;  or (a && b) |-> # #2 C; (a && B) |-> # #3 C;

EndProperty

Definition of the clock in the assertion: In general, the clock is defined in the property, and it is better to ensure that the sequence is independent of the clock. Of course, from a grammatical point of view, clocks can be defined in Property,sequence,assert

In However, after the assert defines the clock, the property can no longer redefine the clock.

Sequence s5a;

A # #2 B;

Endsequence

Property p5a;

@ (Posedge clk) s5a; Defining clocks in the property

EndProperty

A5a:assert property (P5A); Assert no longer defines the clock

Assertions are implied by the implication operator as the trigger condition of the assertion, overlapping implication: "|->" to indicate that the subsequent operator (the implied expression) is judged at the same time as the antecedent operator (the expression preceding the implication).

Non-overlapping implication: "|=>" to indicate that the antecedent operator in the next moment of validity to judge the subsequent operators.

Property P8; Property p9;

@ (Posedge CLK) a |-> b;     At the same time @ (Posedge clk) a |=> b; Delay a clock

EndProperty EndProperty

SVA description (i)