The difference between FIFO and GPIF

What is FIFO

(First Input first Output, FIFO queue) This is a traditional sequential execution method in which the first entry instruction is completed and retired, followed by the second instruction.

1. What is FIFO.
FIFO is the initials of the English first in, is a FIFO data buffer, he and ordinary memory is not the difference between the external read and write address lines, so it is very simple to use, but the disadvantage is that only sequential write data, sequential reading data, The data address is automatically added 1 by the internal read-write pointer, and cannot be read or written to a specified address by the address line as normal memory.

2. What is the case with FIFO.
FIFO is generally used for data transmission between different clock domains, such as one end of the FIFO AD data acquisition, the other end when the computer's PCI bus, assuming that its ad acquisition rate of 16-bit 100K SPS, then the amount of data per second is 100kx16bit=1.6mbps, While the PCI bus speed is 33MHz, the bus width of 32bit, its maximum transmission rate is 1056Mbps, in two different clock domains can be used as a data buffer FIFO. In addition, for different widths of the data interface can also be used FIFO, such as single-chip camera 8-bit data output, and DSP may be 16-bit data input, in the microcontroller and DSP connection can use FIFO to achieve data matching purposes.

3. Some important parameters of FIFO
The width of the FIFO: in the English data is often seen in the width, it is only a FIFO read and write data bits, like the MCU has 8-bit and 16-bit, ARM 32-bit, etc., the width of the FIFO is fixed in a monolithic finished IC, there are also selectable, If a FIFO is implemented by FPGA itself, its data bits, that is, the width, can be defined by itself.

FIFO Depth: The deepth, which refers to how many n bits of data the FIFO can store (if the width is n). such as a 8-bit FIFO, if the depth of 8, it can store 8 8 bits of data, depth of 12, you can store 12 8 bits of data, the FIFO depth can be small, the individual think the FIFO depth calculation does not have a fixed formula. In the FIFO actual work, the full/empty flag of its data can control the continuation of the data write or read out. In a specific application it is also not possible to count the number of parameters of the exact required FIFO depth, which is more than the ideal state of writing speed than the reading speed is feasible, but in practice the FIFO depth is often greater than the calculated value. In general, according to the specific situation of the circuit, in the case of system performance and FIFO cost estimates a approximate width and depth can be. For applications where write speed is slower than reading speed, the depth of FIFO is determined by the specific requirements of the readout data structure and readout data.
Full flag: A signal sent by the FIFO state circuit when the FIFO is full or will be full, to prevent the FIFO from continuing to write data to the FIFO (overflow).
NULL flag: A signal sent by the FIFO state circuit when the FIFO is empty or will be empty to prevent the read operation of the FIFO from continuing to read data from the FIFO resulting in invalid data readout (underflow).
Read clock: Reads the clock followed by the read operation, reading the data when each clock is coming along.
Write clock: The clock that the write operation follows, writing the data as each clock comes along.
Read pointer: Points to the next read-out address. Automatically add 1 when you finish reading.
Write pointer: Point to the next address to write, finish automatically add 1.
Read-write pointers are actually read-write addresses, but this address can not be arbitrarily selected, but continuous.

4. Classification of FIFO
The clock domain in which the root is FIFO, can be divided into synchronous FIFO and asynchronous FIFO. The synchronous FIFO refers to the read clock and the write clock for the same clock. Read and write operations occur at the same time along the clock. Asynchronous FIFO refers to the read-write clock inconsistency, and read-write clock is independent of each other.

5. The difficulty of FIFO design
The difficulty of FIFO design is how to judge the empty/full state of FIFO. In order to ensure that the data is correctly written or read out without the benefit or the state of the read empty, it is necessary to ensure that the FIFO is full and the write operation cannot occur. The read operation cannot be performed in an empty state. How to judge the full/empty FIFO becomes the core problem of FIFO design. Because the synchronization FIFO is rarely used, only the empty/full flag of the asynchronous FIFO is described as having problems.
In the design of the trigger, it is unavoidable to encounter the problem of metastable state (about metastable state is not introduced here, can see the relevant information). In the circuit involving the trigger, the metastable state cannot be completely eliminated, only to find a way to minimize the probability of its occurrence. One way to do this is to use gray code. Gray code between the adjacent two yards by only one transform (binary code in many cases is a lot of code in the same time change). This avoids metastable phenomena when the counter is synchronized with the clock. But Gray code has a drawback is only to define the depth of 2^n, and not like the binary code as arbitrarily defined FIFO depth, because the gray code must cycle a 2^n, otherwise there is no guarantee of two adjacent code elements between the conditions, so it is not the real each of the Thunder code. The second is the use of redundant triggers, assuming that a trigger has a metastable probability of p, then the two and the associated trigger metastable probability is the square of P. But this leads to an increase in latency. The occurrence of metastable state will make the FIFO error, and the read/write clock sample address pointer will be different from the real value, which causes the address error to be written or read out. Due to the effect of delay, the generation of the empty/full flag does not necessarily occur when the FIFO is really empty/full. An empty/full flag may appear when the FIFO is not empty/full. This is not bad, as long as the FIFO does not appear overflow or underflow is OK.
Many of the FIFO articles are actually talking about the different algorithm problems of empty/full flags.
In the article "Asynchronous FIFO structure" of Vijay A. Nebhrajani, the author presents two algorithms for FIFO empty/full flags.
The first algorithm constructs a FIFO with a pointer width of n+1 and a depth of 2^n bytes (converts a gray code pointer to a binary pointer for a comparison of the sides). When the top of the binary code of the pointer is inconsistent and the other n bits are equal, the FIFO is full (in Clifford E. Cummings's article The Gray code is the first two bits are not the same, then the two-bit LSB is the same full, which is the same as the MSB in binary notation is different from the same as full). When the pointer is exactly equal, the FIFO is empty. This may not be easy to see, for example: How a FIFO with a depth of 8 bytes works (using a pointer that has been converted to binary). Fifo_width=8,fifo_depth= 2^n = 8,n = 3, the pointer width is n+1=4. At first Rd_ptr_bin and wr_ptr_bin were "0000". A 8-byte data is written to the FIFO at this time. Wr_ptr_bin = "rd_ptr_bin=", "0000". Of course, this is the full condition. Now, suppose that 8 reads were performed, making rd_ptr_bin = "1000", which is the null condition. Another 8 writes will cause Wr_ptr_bin to be equal to "0000", but Rd_ptr_bin is still equal to "1000", so the FIFO is full condition.
Obviously the start pointer does not need to be "0000". Assuming it is "0100" and the FIFO is empty, then 8 bytes will make Wr_ptr_bin = "1100", and Rd_ptr_bin remains "0100". This also indicates that the FIFO is full.
In Vijay A. Nebhrajani this "asynchronous FIFO structure" article explains how to use the gray code to set the condition of empty full, but did not say why the depth of 8 FIFO its read-write pointer to the 3+1 bit of gray code to achieve, and 3+1 bit of gray code can represent 16-bit depth, And the real FIFO is only 8 bits, and that's what's going on. And this question is explained in Clifford E. Cummings's article. Three-bit gray code can represent the depth of 8 bits, if in addition to the most MSB, then this bit plus the other three-bit gray code does not represent the new address, that is, the gray code of 0100 represents 7, and 1100 still represents 7, But Gray code in a 0-bit MSB after the loop into a 1-MSB loop, and then into a 0-bit MSB loop, the other three-bit code is still gray code, but this brings a problem, after the completion of the 0100 cycle, into 1000, they have two bits between them have undergone a transformation, Instead of 1 bits, so adding a MSB to the code in two places: 0100~1000,1100~0000 has a two-bit code change, so the code is not the real gray code. The added MSB is for the calculation of empty full flags. Vijay A. Nebhrajani article with gray code to binary, and then to the case of the Gray code to put forward empty conditions, only two conversions, and Clifford E. Cummings in the article directly under the Gray code condition to obtain the empty full condition. In fact, the two are the same, but the way of implementation is different.

The second algorithm: the style #2 mentioned in Clifford E. Cummings's article. It divides the FIFO address into 4 parts, each with a height of two bits of MSB 00, 01, 11, 10 to determine whether the FIFO is going full or going empty (about to fill or blank). If the high two-bit MSB of the write pointer is less than the read pointer of the high two-bit MSB then the FIFO is "almost full",

If the high two-bit MSB of the write pointer is greater than the read pointer, the high two-bit MSB is "almost Empty" FIFO.


A method is also mentioned in the third part of the asynchronous FIFO structure of Vijay A. Nebhrajani, which is the direction sign and threshold. Set the FIFO capacity of 75% as the upper limit, set the FIFO capacity of 25% is the lower limit. When the direction flag exceeds the threshold, the full/empty flag is output, which is #2可谓是异曲同工 with the style mentioned in Clifford E. Cummings's article. They all belong to the conservative empty-full judgment. In fact, the output empty full flag FIFO is not necessarily really empty/full.
In this regard, we have clearly seen that the most critical FIFO design is the creation of an empty/full flag of the different algorithms produced a different FIFO. However, whether the precision of the empty full or conservative full is to ensure that the FIFO work is reliable.

GPIF (General programmable Interface), which is a universal programmable interface, is a user-programmable interface designed by Cypress Company in its EZ-USB FX and FX2 series microcontroller, with fast and flexible features, A variety of protocols can be used to complete the seamless connection with peripheral devices, such as Eide/atapi, IEEE1284, Utopia and so on. It can be programmed on demand and does not require CPU intervention in operation, only with some CPU flags and interrupts to communicate with the enhanced 8051 kernel.

GPIF way, Inside is a master, and to control the periphery is a slave,
Read-write signals and some control signals are sent by FX2; the periphery only provides you with a handshake signal connected to your RDYX signal, which is used to control the waveform;

FIFO mode, your peripheral is as master, and FX2 as a slave, read and write signals are provided by the periphery. FX2 do some configuration work.

As for the pros and Cons: Gpif way, the firmware is a bit more complicated. Of course, it's not hard if you learn it. On the first use of the words, feel a bit complicated, because it involves the GPIF waveform problem, and the design of this waveform, there are some fastidious. Of course, you can download it online to a document that is specifically designed to explain the GPIF waveform.

In addition, the speed of GPIF theory is higher than the slave FIFO.

SLAVE FIFO mode, you are writing the firmware is relatively simple. Well ..., more work on the periphery. In addition, his theoretical speed is not GPIF high.