The module test function is based on linux2.6.

# Include <Linux/init. h>

# Include <Linux/module. h>

# Include <Linux/kernel. h>

Static int hello_init (void)

{

Printk ("... \ n ");

Return 0;

}

Static void hello_exit ()

{

Printk ("...");

}

Module_init (hello_init );

Module_exit (hello_exit );

 

Module_license ("dual BSD/GPL );

 

MAKEFILE file:

OBJ-M: = test. o

Kdir: =/lib/modules/$ (shell uname-R)/build $ (kdir) specifies the path of the kernel source code. "m =" indicates that this is an external module, M = $ (PWD) specifies the path of the module File.

PWD: = $ (shell PWD)

Default:

$ (Make)-C $ (kdir) subdirs = $ (PWD) Modules

Clean:

Rm-RF *. Ko

Rm-RF *. Mod .*

Rm-RF. *. cmd

Rm-RF *. o

Insmod test. Ko, rmmod test. Ko

If multiple source files are compiled into one module and the module name is test. Ko, the source file name cannot contain test. C. Note: For details about the compilation module in section 2.6, refer to Linux/documentation/kbuild/modules.txt.

 

Ifneq ($ (kernelrelease ),)

OBJ-M: = mytest. o

Mytest-objs: = file1.o file2.o file3.o

Else

Kdir: =/lib/modules/$ (shell uname-R)/build

PWD: = $ (shell PWD)

Default:

$ (Make)-C $ (kdir) M = $ (PWD) Modules

Endif

Explanation:

Kernelrelease

It is a variable defined in the top-level makefile of the kernel source code. When this makefile is read for the first time, kernelrelease is not defined,

Therefore, make will read the content after else execution. If the target of make is clean, directly execute the clean operation and end. -C

$ (Kdir) indicates to jump to the kernel source code directory to read the makefile; m =$ (PWD)

Indicates that the current makefile will be read and executed in the current directory. When returned from the kernel source code directory, kernelrelease is defined and kbuild is also started.

Make will continue to read the content before else by parsing the kbuild syntax statement. The statement before else is the kbuild syntax,

Specify the dependency between each file in the module source code and the name of the target module to be generated. Mytest-objs: = file1.o file2.o

File3.o indicates that mytest. O is generated by connecting file1.o, file2.o, and file3.o. OBJ-M: =

Mytest. O indicates that the mytest. O module is generated after the connection is compiled.

The makefile of the Linux kernel is divided into five parts:

Makefile top-level makefile
. Config Kernel configuration file
ARCH/$ (ARCH)/makefile of the specific architecture
Scripts/makefile. * general rules. For all kbuild makefiles.
There are about 500 such files in the source code of the kbuild makefiles kernel.

The. config file read by the top-level makefile, which is generated by the Kernel configuration program.
The top-level makefile is responsible for the preparation of vmlinux (kernel files) and modules (any module files ). The production process is mainly
Recursively accessing sub-directories. Determine which subdirectories to access based on the Kernel configuration file. Top layer
Makefile must be a specific makefile of a specific architecture. Its name is similar to arch/$ (ARCH )/
Makefile. This architecture makefile provides the top-level makefile with special information about its architecture.
Each subdirectory has a kbuild MAKEFILE file to execute commands passed from its upper directory.
Kbuild makefile extracts information from the. config file and generates a list of files required for kbuild to complete kernel compilation.
Scripts/makefile. * contains all definitions, rules, and other information.

The target definition is the main and core part of kbuild makefile. It mainly defines the files to be compiled, all the options, and the subdirectories to perform recursive operations.
The simplest kbuild makefile contains only one row:
Example:
OBJ-y + = Foo. o
This example shows that kbuild has a target file named Foo. O in this directory. Foo. O will be compiled from the foo. C or Foo. s file.
If Foo. O is to be compiled into a module, it will use obj-M. The format is as follows:
Example:
OBJ-$ (config_foo) + = Foo. o
$ (Config_foo) can be y (compiled into the kernel) or M (compiled into a module ). If config_foo is not y and m, the file will not be compiled and connected.

 

Kbuild can identify the suffix-objs and suffix-y used to form the target file. Therefore, kbuild makefile can use the config _ symbol to determine whether the object is used to combine objects.

The files listed in obj-* are used to compile the module or connect to the built-in.o in a specific directory. You can also list files that will be included in library Lib.. The files listed in Lib-y are used to form a library file under this directory.