The principle of frequency-locked loop octave operation a personal rough understanding

With s3c2440 clock & power Management As an example, 24,401 can be configured using an external crystal or an external clock as the clock source via Om[3:2]. External Crystal general selection of 12MHZ, and 2440 if the work in this frequency is obviously overqualified, 2440 normal operating frequency up to 400MHZ, obviously from 12MHZ to 400MHZ need octave, 2440 through the phase-locked loop unit to achieve the multiplier.

In this block diagram above, Pfd,pump,loop Filter,vco together to form a phase-locked loop.

1. PFD (phase Detector): Converts the phase difference of the 2 input Fref,fvco to the corresponding control signal output.
2. PUMP
3. Loop Filter
4. VCO (Voltage controlled oscillator): the input voltage controls its output frequency to a certain proportional relationship.

When the 2 input frequency phase difference of the PFD stabilizes, for example, 0 o'clock, after the Pump,loop filter input to the VCO voltage will also be stable, then the output of the VCO is stable, the entire phase locked loop frequency lock, that is, the VCO output frequency is stable. The explanations above may not be accurate, but the entire PLL is like using a negative feedback.

Single See Pfd+pump+loop Filter+vco seems to be able to get a ratio of fref to a certain proportion of the frequency, to achieve the proportion can be set then need to divider, divider. First, the pfd+pump+

Loop Filter+vco as a whole PLL (phase-locked loop), assuming that the fref and VCO output is a 1:1 relationship, in order to stabilize the PLL, then fref and Fvco must be equal, assuming divider m is 10-way, Then the stable VCO output frequency will be fref 10 times times, the multiplier effect is achieved.

The principle of frequency-locked loop octave operation a personal rough understanding