Timing analysis in FPGA (II.)

using Timequest

I am more familiar with Altera, here with Quartus II in the Timequest as explained.

The core of the Timequest analysis sequence is the calculation of the delay factor. Then establish the constraint file, to tell Timequest, which place has what kind of constraint, how to constrain.

The reason to establish the related network table concept, because we use Quartus II in the Timequest, the approximate process is: the establishment of the network table----The establishment of SDC file----Update network table;

2.1 SDC Web Table

The SDC Web table includes: port, PIN (PIN), Unit (cell), net (net), which can explain the concepts of the various parts.

Then we will use Timequest, as with the use of Signaltap II, before using to establish an SDC file, the file name can be arbitrary, the recommendation is the same as the module name. Then save it as the name you named.

2.2 Establishment of timing netlist

Then before using the Timequest, the first to compile the source files, set up a good fit file before you can, please note!!!

Then click the Timequest button to enter into the Timequest, as shown below,

The above three commands are more important commands, the first is to create a Web table, start cabling, establish a hard model, the second is to read the SDC file, the third is to update the Web table, whenever there is a change, need to update.

Figure 16.5 Adaptation situation

Above the Post-fit, closer to the physical model, after optimization,

Above the Post-map, is not optimized, closer to the prototype.

Will ignore the delay of some of the basic unit of the Web table.

On the suitability of a better case or a poor fit situation, the design to set, the general worst case can be passed, then the better the situation will certainly be able to pass.

In general, figure 16.5 is sufficient. This is also the result of double-clicking. Of course, you can manually set it, that is.

2.3 Setting up SDC files

Note that the above clock name is the same as the global clock network name, targets here Select the Global clock network you set.

Select Get_ports and click the list button to select the clock signal. To constrain other signal methods.

After the constraint has been established, read the SDC file, there are two ways to read SDC, (1) can be set in setting, as shown in.

(2) You can also read the file in Timequest, click Constraints in the Timequest interface----Read SDC file, as shown in.

2.4 Updating the Grid table list time series diagram

Update the Web table file. Then double-click, you can see our constraint content on this signal, right click, you can report timing, figure 16.6 is the interface of the reporting time series, the first from the source clock to the destination clock, this figure 16.7, will be associated with the Register node involved.

Figure 16.6 Operator Interface

For the from clock and to clock in, just given a parameter, it will be associated with the clock related to the involved.

It is also important to note that the number of paths here, if the number of nodes is more, then you need to change the number of paths here, to analyze the relationship between the number of paths. Alternatively, you can double-click the command shown,

However, this method can only achieve 1000 path analysis, if you want to change, you need to manually change the Tcl script file,

Change the 1000 to a larger number in order to complete more path analysis.

Figure 16.7 Register-related node graph

Here you can see if the build and hold allowances meet the requirements, as shown in 16.8.

Figure 16.8 the remainder view

Then the purpose of timequest is to tell the hardware that you are bound to a certain signal, for a given different form of grid, the allowance is also different, the worst case than give the best situation given more margin. Fmax, the highest frequency, this frequency is the longest time to evaluate the length of the clock, but also the largest delay of the line, the maximum frequency can be reached, generally hope that the larger the Fmax the better.

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Timing analysis in FPGA (II.)