Transplantation of U-boot 1.1.6 Based on 44b0
By zenf E-mail: zenf_zhao@163.com
Copyright: The author retains the copyright of any original text and original images in the document. Any reproduction or commercial use must be permitted and authorized by the author. (March October 2007)Note 1: This document is based on the hfrk-based development board configuration platform of the arm744b0.
Note 2: The transplantation of U-boot 1.1.6 is based on the hfrk U-boot 1.1.1 of ARM7 and the appropriate files can be extracted from the packages that can work normally and merged into U-boot 1.1.6, modify the makefile implementation as needed. Contents
1.1 Add a new board for U-boot Step 1
1.2 Add the board type and modify the files in the directory as appropriate 2
1.3 modify the directory file of CPU/B0 and drive the 10 M Ethernet chip 2
1.4 modify the main MAKEFILE file (solving-MQ problems) 3
1.5 compile and run 5
1.6 using Ram to run U-boot to burn New U-boot to flash (dangerous) 10
1.7 Appendix 1: hfrk flash operations 11
1.8 Appendix 2: extract the unassemble part from U-boot 1.1.6 12 1.1 Add a new board for U-boot
This section extracts the README file from the root directory of U-boot 1.1.6 (which can be referenced at will) as the basis for adding a new board. For details, refer to the attachment. 1.2 Add the board type and modify the files in the directory as appropriate
Copy all the content in the Board/hfrk of U-boot 1.1.1 to the Board/hfrk of U-boot 1.1.6. There are two directories: Board/hfrk/common and board/hfrk/hfrkiniti44b0. Copy the Board/Dave/b2/makefile to the Board/hfrk/hfrkjx44b0/makefile to overwrite the original file, and modify the overwritten makefile as follows:
The original makefile line 32/33 is
Cobjs: = b2.o flash. o
Sobjs: = lowlevel_init.o
To:
Cobjs: = hfrkjx44b0. O flash. o
Sobjs: = memsetup. o Copy the include/configs/hfrkcloud44b0. h file in U-boot 1.1.1 to include/configs/hfrkcloud44b0. h in U-boot 1.1.6. 1.3 modify the directory file of CPU/B0 and the driver of 10 M Ethernet chip
Copy the CPU of U-boot 1.1.1. c file to the CPU/3c44b0/serial in U-boot 1.1.6. c overwrite. This copy process modifies serial. in C, configure config_jx44b0_clock_speed = 60. Or you can modify the Compare and merge Based on source code comparison software (such as beyond compare. Modify start. s as follows:
(1) locate the BL lowlevel_init code in line 3 and change it to BL memsetup. This modification uses the memory Initialization Configuration designed by hfrk. (2) Find the following code in line 3:
If config_jx44b0_clock_speed = 66
LDR r0, = 0x34031/* 66 MHz (quartz = 11 MHz )*/
# Elif config_jx44b0_clock_speed = 75
LDR r0, = 0x610c1/* B2: xtal = 20 MHz fclk = 75 MHz */
# Else
# Error config_89c44b0_clock_speed undefined
# Endif
Change to: (ADD and modify the red part, use clock_speed = 60)
# If config_jx44b0_clock_speed = 60
LDR r0, = 0x88042/* 60 MHz (quartz = 10 MHz )*/
# Elif config_jx44b0_clock_speed = 66
LDR r0, = 0x34031/* 66 MHz (quartz = 11 MHz )*/
# Elif config_jx44b0_clock_speed = 75
LDR r0, = 0x610c1/* B2: xtal = 20 MHz fclk = 75 MHz */
# Else
# Error config_89c44b0_clock_speed undefined
# Endif Find the drivers/rtl8019.c Drivers/rtl8019.h files in U-boot 1.1.6, and compare them with rtl8019.h and rtl8019.c in U-boot 1.1.1, change to the 16-bit operating mode of the '10 M Ethernet chip of RTL8019 in U-boot 1.1.1. In rtl8019.h, the address offset is mainly modified as follows:
# Define rtl8019_reg_00 (rtl8019_base + (0x00 <1 ))
# Define rtl8019_reg_01 (rtl8019_base + (0x01 <1 ))
# Define rtl8019_reg_02 (rtl8019_base + (0x02 <1 ))
# Define rtl8019_reg_03 (rtl8019_base + (0x03 <1 ))
# Define rtl8019_reg_04 (rtl8019_base + (0x04 <1 ))
# Define rtl8019_reg_05 (rtl8019_base + (0x05 <1 ))
# Define rtl8019_reg_06 (rtl8019_base + (0x06 <1 ))
# Define rtl8019_reg_07 (rtl8019_base + (0x07 <1 ))
# Define rtl8019_reg_08 (rtl8019_base + (0x08 <1 ))
# Define rtl8019_reg_09 (rtl8019_base + (0x09 <1 ))
# Define rtl8019_reg_0a (rtl8019_base + (0x0a <1 ))
# Define rtl8019_reg_0b (rtl8019_base + (0x0b <1 ))
# Define rtl8019_reg_0c (rtl8019_base + (0x0c <1 ))
# Define rtl8019_reg_0d (rtl8019_base + (0x0d <1 ))
# Define rtl8019_reg_0e (rtl8019_base + (0x0e <1 ))
# Define rtl8019_reg_0f (rtl8019_base + (0x0f <1 ))
# Define rtl8019_reg_10 (rtl8019_base + (0x10 <1 ))
# Define rtl8019_reg_1f (rtl8019_base + (0x1f <1 )) In rtl8019.c, the two register configurations for initialization are modified:
Put_reg (rtl8019_multiaddress0, 0x00 );
Put_reg (rtl8019_multiaddress1, 0x41 );
Put_reg (rtl8019_multiaddress2, 0x00 );
Put_reg (rtl8019_multiaddress3, 0x80 );
Put_reg (rtl8019_multiaddress4, 0x00 );
Put_reg (rtl8019_multiaddress5, 0x00 );
Put_reg (rtl8019_multiaddress6, 0x00 );
Put_reg (rtl8019_multiaddress7, 0x00 ); 1.4 modify the main MAKEFILE file (solution-MQ problem)
In makefile, add the hfrkjx44b0 card, find the systems, and add the following after the b2_config Board:
######################################## ##
# Hfrk s44b0 Systems
######################################## ###
Hfrks344b0_config: unconfig
@ $ (Mkconfig) $ (@: _ Config =) arm cloud44b0 hfrkcloud44b0 hfrk Modify the prefix of the Cross-compilation tool of makefile, find the compiling prefix of arch arm, and change arm-Linux-to arm-elf-as follows:
Ifeq ($ (ARCH), arm)
# Cross_compile = arm-Linux-
Cross_compile = arm-elf-
Endif The following changes solve the problem of MQ compilation control in makefile. Because the arm-elf-GCC compiler used by the author is based on the old hfrk version, it is somewhat compatible with-MQ control options, due to my limited ability, I used makefile and config. make appropriate modifications to the content in mK to ensure compilation is successful. (This document will be updated later when I find a simpler makefile solution) For details, refer to the attachment. 1.6 how to run U-boot to burn New U-boot to flash based on RAM (dangerous)
You can use JTAG to burn U-boot to flash. You need to enable JTAG, parallel port, and ads project. In my family work, The Flash programmer is used for the first time when the boot content of all device boards is burned out from the factory, and all subsequent burn writes are automatically upgraded by software. (I plan to add the automatic U-boot upgrade function for U-boot in the future) The hfrk-based U-boot Operation Flash command and related instructions, we can automatically write the new U-boot into FLASH based on U-boot. First, based on the flash U-boot, press any key to enter the Script Mode, run the TFTP Command, load the newly compiled u-boot.bin to the RAM memory 0xc008000 address space. For example, in the loading process of 1.5, the file length is 143684, 0x23144/4 + 2 = 0x8c54. Second, run the erase command to erase the U-boot storage area of flash. Run the following command:
Erase 0x00 0x3ffff Finally, use the CP command to write the new U-boot in the RAM memory to flash:
CP 0x000 0xc008000 0x8c54 Note 1: because the new U-boot upgrade process is more professional, and there may be exceptions in the process, it is recommended not to use this method if you are not very skilled. The user-related problems are caused by the upgrade of the U-boot mode. NOTE 2: the system cannot be started because the flash U-boot fails to be upgraded, it is recommended that the reader load the newly compiled U-Boot Based on TFTP and upgrade it after it can be used normally (for example, it is similar to the test process passed in 1.5.
1.7 Appendix 1: Flash operation instructions for hfrk For details, refer to the attachment.
1.8 Appendix 2: unassemble part Excerpt from U-boot 1.1.6
For details, refer to the attachment.
U-boot: File Format elf32-littlearm Disassembly of section. Text: 0c700000 <_ Start>:
C700000: ea00000a B c700030 <reset>
C700004: e28ff303 add PC, PC, #201326592; 0xc000000
C700008: e28ff303 add PC, PC, #201326592; 0xc000000
C70000c: e28ff303 add PC, PC, #201326592; 0xc000000
C700010: e28ff303 add PC, PC, #201326592; 0xc000000
C700014: e28ff303 add PC, PC, #201326592; 0xc000000
C700018: e28ff303 add PC, PC, #201326592; 0xc000000
C70001c: e28ff303 add PC, PC, #201326592; 0xc000000 0c700020 <_ text_base>:
C700020: 0c700000 ldceql 0, Cr0, [R0] 0c700024 <_ armboot_start>:
C700024: 0c700000 ldceql 0, Cr0, [R0] 0c700028 <_ bss_start>:
C700028: 0c72314c ldfeqe F3, [R2],-#304 0c70002c <_ bss_end>:
C70002c: 0c757ec8 ldceql 14, cr7, [R5],-#800 0c700030 <reset>:
C700030: e10f0000 Mrs r0, CPSR
C700034: e3c0001f Bic r0, R0, #31; 0x1f
C700038: e3800013 Orr r0, R0, #19; 0x13
C70003c: e129f000 MSR cpsr_fc, R0
C700040: eb1_1a BL c7000b0 <cpu_init_crit>
C700044: eb000056 BL c7001a4 <memsetup> |
