Use Modelsim to simulate the SDRAM operation

I wrote two blogs about Modelsim simulation. The naming of the module PINs may be a bit strange. In fact, the previous two articles are designed to simulate the SDRAM operation.

Because the simulation process of SDRAM is relatively complicated and cumbersome. Therefore, more than one blog may be required.

 

Before starting the simulation, if you are not familiar with the principle and timing of SDRAM, we recommend that you read the following article:

SDRAM-master advanced and ultimate memory Technical Guide-complete advanced Edition

 

OK. The simulation process is officially started below.

By looking at the memory technical guide, we can summarize the working process of the SDRAM:

 

1. Enter the input stabilization period of us after power-on, empty operation (NOP)
2. Send the precharge command once (one clock cycle) to the SDRAM, and then keep n NOP operations in the clock cycle (N values can be found in the specific SDRAM chip manual of the chip, it is related to the clock frequency of the SDRAM operation)
3. Send the refresh command eight times to the SDRAM. The specific sending process will be described later.
4. Set the SDRAM working mode register
5. After initialization, you can start read/write operations.

PS: In addition to the above operations, there is also a periodic operation that is self-Refresh. For the chips I use, we need to perform a self-Refresh operation every 15 us. (15us * 4096 = 61.44 Ms <64 ms. Please refer to the ultimate memory Technical Guide for this setting) certificate ------------------------- $ $ $ response --------------------------------------------------------------------------------------------------------------- ------------------------------------------ Paste several initialization-related images below: Mode register settings !!! The value of my mode register is 0x023. As you can see, my options are as follows:

• Operation Mode: burst read/write
• Latency: two clock periods
• Burst transmission mode: Sequence
• Burst length: 8 (SDRAM chip: 4 blocks, 1 m * 16 bit, 64 Mbit in total) therefore, the burst length 8 indicates that the data volume transmitted for each read or write command is 8 * bit width = 8 * 16bit = 128bit = 16 bytes (the data mask dqm is not considered for the time being)

Certificate ------------------------- $ $ $ begin ---------------------------- The simulation process involves the PLL module and the FIFO module. For the simulation of these two modules, refer to the previous two blogs. The complete system source code is from the blog of privileged students, which can be downloaded to the source code. First, to make it easier to observe the simulation waveform, list the SDRAM commands first.

SDRAM command

	Cke	Cs_n	Ras_n	Cas_n	We_n
Null operation (NOP)	1	0	1	1	1
Pre-Charging)	1	0	0	1	0
Refresh	1	0	0	0	1
Valid row	1	0	0	1	1
Start read	1	0	1	0	1
Start writing	1	0	1	0	0
Mode register settings	1	0	0	0	0

(The signal at the end of PS: _ n indicates that the low level is valid.) waveform 1: The Red waveform after the PLL completes Initialization is a command-related signal. I put them in a group for easy observation. We can see that at, the clock effective signal cke becomes higher, the chip selection signal cs_n becomes lower, and the SDRAM starts to act. Refer to the command table, the startup command of SDRAM is 10111, that is, the NOP operation. This process should last nearly us, which is called the input stability period.

Waveform 2: pre-charge, corresponding to command 10010 and 8 refresh operations, corresponding to command 10001, note that each command is followed by a period of Nop operations, which makes the SDRAM have time to execute commands. Waveform 3: Mode register settings. You can see that the command is 10000, in this case, the values of sdram_ba [1:0] And the address line sdram_addr [] are 0 and 0x033, respectively. (My real device uses 0x023. The simulation result is incorrect, but it does not affect the waveform reading. From this figure, we can clearly see that the clock frequency of the SDRAM is 100 MHz, and there is a phase difference with the MHz clock of the fpga sdram Controller. This is necessary. The reason is that the command is generated when the clock rising edge of the SDRAM controller is generated, and then the command is stable when the clock rising edge of the subsequent SDRAM is obtained, so that the command can be obtained smoothly. The same is true for data transmission. In the simulation, the phase difference I selected is 72-degree waveform 4: Write the SDRAM data. Combined with the FIFO operation in the previous article, this waveform should be easy to understand. The last two rows: sys_data_in is the data transmitted by the FIFO to the SDRAM control module, and sdram_data is the data bus of the SDRAM. there is a delay in the clock period between the two. It can be seen that the SDRAM Controller first issues a valid command (10011), selects 0th lines of 0th logical blocks, and then sends a write command (10100) after two clock cycles ), the column address is 0, and the first data 0x0000 is placed on the data bus of the SDRAM without delay. After this command is executed, eight 16-bit data entries are written, this corresponds to the burst length mentioned above. In addition, a careful friend can see that when writing a command, the address line value is 0x400, 4 corresponds to A10, set 1 to allow automatic pre-charging. So what is automatic pre-charging? After each read operation, the data whose logic is 1 is read and discharged, which may change to 0. Therefore, data needs to be written, ensure that the value after reading is not lost. Therefore, automatic pre-charging is quite necessary. Waveform 5: 15 us self-Refresh .. Corresponds to command 10001. It can be seen that, once the SDRAM starts to run, the self-Refresh will be distributed throughout the entire lifecycle of the SDRAM, 15 us at a time, not much. This is the source of motivation for maintaining the stability of SDRAM. OK. Here is the Modelsim simulation of the SDRAM. Why don't we introduce the read simulation of SDRAM? :) Begin ------------------------- $ $ $ close -------------------------- Download the simulation source code of the entire system (including simulation of the PLL, FIFO, data_generator module): Download the source code of the Modelsim simulation SDRAM project to add the required files to the project and modify the system. do file, and then execute. (ALL. Do files are stored in the Modelsim folder.) The Modelsim version I use is se10.0c. The simulation files required for this project are as follows: Source: http://blog.csdn.net/ruby97/article/details/7356110

Use Modelsim to simulate the SDRAM operation