The I/O is a channel for CPU and peripheral communication, mainly divided into two types, port I/O, and Mmio (Memory mapping I/O). The
is the I/O port that we often call, and it should actually be called the I/O address space. The
is accessed through the In/out directive for the x86 schema. The PC architecture has a total of 65,536 8bit I/O ports, consisting of the 64ki/o address space, numbered from 0~0XFFFF. Two consecutive 8bit ports can be composed of a 16bit port, 4 consecutive ports composed of a 32bit. The physical address space of the I/O address space and the CPU is two different concepts, such as the I/O address space is 64K, and a 32bit CPU physical address space is 4G. The
Mmio consumes the physical address space of the CPU, and access to it can be performed using the instructions of the CPU to access the memory. An image metaphor is to use mmap () to access files like memory, and Mmio accesses I/O resources, such as memory on a device, in the same way that it accesses memory. Mmio can not be cache, reason before many post discussed, not much said (there are special cases, such as VGA). The main difference between
Port I/O and Mmio is that 1) does not occupy the physical address space of the CPU, which is owned (this is said for the x86 architecture, some architectures, such as Ia64,port I/O occupy Physical address space). 2) The former is sequential access. This means that the next instruction will not be executed until an I/O instruction is complete. For example, the operation was initiated through port I/O to the device, causing a change in the device register state, which takes effect before the next instruction is executed. The Mmio of the Uncache is guaranteed to be sequential by UNCAHCE memory characteristics. 3) use different
because the port I/O has a separate 64ki/o address space, but the address line of the CPU is only one set, it must be distinguished whether the address belongs to the physical address space or the I/O address space. The early CPU had a m/i pin to represent the type of the current address, which later seemed to change. Just looked up, called request command line, did not understand, think still a stitch. The
IBM PC architecture Specifies fixed I/O ports, and ISA devices often have fixed I/O ports, which can be found through the ICH (South Bridge) specification. The I/O port of the PCI device and the Mmio base address are reported to the operating system via the PCI configure space of the device, which has many previous posts and can be consulted. IOMMU Architecture
Iommu is for the device to initiate the DMA operation, you can understand that the device used to do the DMA address is a virtual address (this virtual address and we usually say that the same, is specifically the device DMA with the address, relative to the real physical address.) The physical address is used without IOMMU).
AMD,INTEL,SUN,IBM have launched their own IOMMU technology, Pci-sig Association has also carried out the relevant work, |
