Xilinx FPGA LVDS Applications

The recent project needs to use differential signal transmission, so we look at the use of differential signals on the FPGA. In Xilinx FPGAs, differential signals are sent and received primarily via primitives: Obufds (differential output buf), Ibufds (differential input buf).

Note that when assigning pins, only the pins of the signal_p are assigned, and the Signal_n is automatically connected to the respective differential pair pins, without the LVDS option on the pin level (IO planning PlanAhead) If the differential signal primitive is not used.

Test code:

//////////////////////////////////////////////////////////////////////////////////Modulelvds_test (SYS_CLK, Sys_rst, Signal_in_p,                                                Signal_in_n, Signal_out_p, Signal_out_n, led_signal);inputSys_clk,sys_rst;inputSignal_in_p,signal_in_n;OutputSignal_out_p,signal_out_n;Outputled_signal; Wiresignal_out_temp;Reg[ to:0] clk_cnt; always@ (PosedgeSYS_CLK)begin    if(!sys_rst) clk_cnt <= +'D0;    Else begin        if(clk_cnt = = +'d10_000_000) clk_cnt <='D0; Elseclk_cnt <= clk_cnt+1'B1;    EndEndAssignsignal_out= (clk_cnt >= +'d5_000_000)? 1:0;Obufds Signal_out_diff (. O (signal_out_p),. OB (Signal_out_n),. I (Signal_out)); Ibufds Signal_in_diff (. O (led_signal),. I (Signal_in_p),. IB (Signal_in_n));Endmodule

Constraint file:

NET"signal_out_p"Iostandard =lvds_33;net"signal_out_p"LOC =u16;net"SYS_CLK"Iostandard =lvcmos33;net"Sys_rst"Iostandard =lvcmos33;net"led_signal"LOC =d18;net"led_signal"Iostandard =LVCMOS33, #Created by Constraints Editor (xc6slx45t-csg324-3) - ./ ./ .NET"SYS_CLK"Tnm_net ="SYS_CLK"; Timespec TS_SYS_CLK= PERIOD"SYS_CLK"  -MHz High -%; NET"signal_in_p"LOC =t12;net"Signal_in_n"LOC =v12;net"SYS_CLK"LOC =g8;net"Sys_rst"LOC =u3;# PlanAhead Generated IO constraints NET"signal_in_p"Iostandard = lvds_33;

Constraint file IO planning planahead generation, the use of primitive language can be consulted: E:\Xilinx\ISE\14.7\ISE_DS\ISE\doc\usenglish\isehelp\spartan6 inside provides the original language of the device used. A 100 ohm resistor match is also provided inside the Xilinx device internal signal for reference to the Spartan-6 FPGA SelectIO Resources (UG381)

Xilinx FPGA LVDS Applications