Xilinx High-speed transceiver serdes in-depth research

Why use Serdes

Traditional source synchronous transmission, clock and data separation. When the rate is relatively low (<1000M), there is no problem.

This can be problematic at higher and higher rates

Due to the inconsistent delay and jitter of the transmission line, the receiving end cannot sample the data correctly, and the points in the eye diagram are not aligned.

Then I thought of recovering the clock from the data to sample the data, that is, the CDR

In this way, there is no inconsistency in delay, and a slight jitter will not affect the sampling (the recovered clock will jitter along with the data).

 Second, why use 8b10b, 64b66b?

 1 provide enough transitions to recover the clock

There is still a problem. The two ends of the transceiver must share the same ground, but it is often difficult to achieve.

So sampling differential signal transmission, in order to prevent the common mode voltage from causing excessive current at the receiving end, the current drive mode is used. It is seen that there is a capacitor at the receiving end for AC coupling and DC blocking. This poses another problem, which requires DC balance. So for another reason. 

2 DC balance, that is, the number of 0 and 1 should be equal.

3 run length, the maximum length of 0 and 1 consecutive occurrences

AGC automatic gain control requires AC components to achieve amplification

The high-speed serial stream on serdes needs to be re-serialized and converted into multi-word 

4 comma code, K code

parallel at the receiving end. How to find the boundaries of the words for alignment.

This requires a special sequence, which is the comma code.
Some control needed in the transmission process, it is best not to conflict with the data, this is the K code.

Based on the above four reasons, 8b10b and 64b66b appeared.

 Third, 8b10b encoding

In a word, 8b10b encoding is to turn 8bit data into 10bit data. The number of all 1s or 0s will not exceed 6 and the number of consecutive 1s or 0s will not exceed 4 In this way, the original 1024 Hamming space coding is greatly reduced. There are 256 data codes and 12K code control codes. In this way, data and control codes do not overlap.

Among them, K28.1, K28.5, and K28.7 can be used as separation codes, also called comma codes, which are used by the receiving end to find byte boundaries in the serial data stream. The commonly used K28.5 is 0xBC. Because normal transmission data may also have 0xBC, how to distinguish it. There is a separate control line, tx_is_K is pulled high when transmitting the K code, and pulled low when transmitting data, to control whether the 8b10b encoding module is encoded into data or controls the K code.

 Fourth, several details of Xilinx Serdes 

1. The use of COMMA code

K28.5,0xBC, + 0101_111100, -1010_000011; It is used to detect byte division.

Use other K codes as frame start, frame end, clock correction and data alignment. 

2. Multi-byte processing

When the data rate is high, the external bit width may be 2 words (16 bits) or 4 words (32 bits). This is if the sender and receiver do not agree on which word to send the comma code, then the word boundary can be detected, but the receiver will have a high and low byte flip. In any data alignment for a single COMMA, select even-numbered byte alignment. When sending, 0x5ABC-> 2’b01.

You can also choose to send the combined comma code, which is to splice the coma of the NP and send it, so that the receiving end detects the 16-bit double word boundary. You can also avoid the above situation. When sending 0xBCBC-> 2’b11

Note: Do not select decode valid comma only, because other K codes may also be sent for control. Anyway, 8b10b is a hard-core resource of the transceiver, so don't use it for nothing. 

3. Loopback settings:

1. "000": Normal mode
2. "001": near-end PCS loopback
3. "010": near-end PMA loopback
4. "100": remote PMA loopback
5. "110": remote PCS loopback

Note that the loopback configured in the Xilinx instantiated example file means that the loopback interface is reserved. It still needs to be manually configured. 

4, fsm_down state machine

In the Monitor Data_Valid module, the correct signal of frame_check is used. Failure to verify will cause GTrxreset to be reset. It can be set directly without this feedback. Need to change it manually. 

5. Channel binding

Limited space, listed separately 

6. Clock correction

Limited space, listed separately