Zero-dead corner game stm32-read excerpt 3

I. ADC (DMA mode)

1. clock frequency settings

The maximum clock frequency of the CPU is 72 MHz, while that of the ADC module is 14 MHz. To achieve the maximum clock frequency of the ADC module, the maximum CPU frequency can only be set to 14 m x 4 = 56 m. (The commonly used clock frequency of pclk2 is 72 MHz, and the adcclk must be lower than 14 MHz. Therefore, in this case, the maximum frequency of adcclk is the 8-frequency division of pclk2, that is, adcclk = 9 MHz. If you want to enable the ADC to run at the highest frequency of 14 MHz, you can configure pclk2 to 56 MHz, and then obtain adcclk by dividing the 4-Digit Frequency .) You can't have both of them! In addition, when using USB, the system clock must be 48 MHz or 72 MHz. In this case, the maximum clock frequency of the ADC module is 48 MHz.
/4 = 12 MHz or 72 MHz/6 = 12 MHz, that is, the maximum sampling rate of the ADC is 857 K/s.

The value of the adc_sampletime parameter is used to configure the sampling period of the current channel. The minimum value can be set to 1.5 sampling periods. The period here refers to the adcclk clock period.

ADC sampling time calculation formula:
Tconv = sampling period + 12.5 cycles
The sampling period in the formula is the adc_sampletime configured in this function, and the 12.5 periods added after the formula are fixed values.

2. self-calibration

Before starting the ADC conversion, you need to start the self-calibration of the ADC. The ADC has a built-in self-calibration mode, which greatly reduces the accuracy error caused by changes in the internal capacitor group. An Error Correction Code (numerical value) is calculated on each capacitor during calibration, which is used to eliminate errors produced on each capacitor in subsequent conversions.