BF531 Notes of DSP

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A long time ago BF531 notes, feel useful to share out. Excerpt from the Open DSP

Universal Gpio

There are 16 PF interfaces on the adsp-bf53x processor, which is the usual IO interface, which can be used as an external interrupt interface for each PF interface through a register configuration.
The IO of the Blackfin processor is different from the MCU, the interface must be initialized before use, such as the direction of the interface, such as the configuration of the output interface, the direct configuration of the output interface level signal, such as the input interface, you need to open the input enable switch, configure the output signal trigger mode, whether interrupt trigger, Whether bipolar triggering and so on. The PF interface cannot be used until initialization is complete.
PF Interface main register function and use method

Example Code Analysis:

 input interface configuration: The PF0 interface is configured as an input interface and the interface level status is read out. *pfio_dir &= ~pf0; //set PF0 as input  *pfio_inen |= PF0; //input enable  i = *pfio_flag_d; //read data  Output Interface configuration: Configure the PF0 interface as an output interface, using two ways to set the PF0 output high and low level. *pfio_dir |= PF0; //set PF0 as output  *pfio_flag_s |= PF0; //pf0 feet high  *pfio_flag_c |= PF0; //pf0 foot low  *pfio_flag_d |= PF0; //pf0 feet high  *pfio_flag_d &= ~pf0; //pf0 foot low   

#gpio中断
The adsp-bf53x 16 PF interface can be used as an external interrupt. To use an external interrupt for PF, you need to select an interrupt source for the PF pin, set the interrupt trigger mode, set an interrupt priority for the interrupt, and enable the interrupt. Fio_maska_d and Fio_maskb_d: Used to set the interrupt source for the PF pin, adsp-bf53x a total of PFA and PFB two interrupt sources, using different interrupt sources by choosing to configure the two registers.
Sic_iarx: Sets the interrupt priority level. Each interrupt source has a default priority level, and if not configured for that register, the interrupt source can be configured with the default interrupt priority level.

It can be seen from the table that the PF pin-related interrupt source PFA and PFB are located in Sic_iar2, its default configuration value is 5, according to its configuration values, the following table to know its corresponding interrupt level is IVG12, such as the SIC_IAR2 configuration value to the values in the following table, The interrupt level becomes the interrupt level corresponding to that value.

Sic_imask: Interrupts the screen register so that it can be interrupted.
Function:
Register_handler (Ik_ivg12, FLAGA_ISR);
The interrupt level management function, defined in the header file "Exception.h", can be used directly after the header file is defined, and its function is to inform the interrupt manager that the break identifier defined is FLAGA_ISR and the interrupt class is level 12.
Ex_interrupt_handler (FLAGA_ISR)
The interrupt function, which is defined in the header file "Exception.h", enters the function execution when the interrupt is triggered.
# #例子代码分析:

PF port setting uses external interrupts: *pfio_inen |= pf0| PF1;//Set PF0,PF1 input Enable*pfio_dir &=~ (pf0| PF1);//Set PF0,PF1 as input interface*pfio_edge |= pf0| PF1;//set to along trigger*pfio_maska_d |= pf0| PF1;//Use the interrupt source as PFA, enable PF external interruptConfigure external interrupts: *PSIC_IAR0 =0xFFFFFFFF; *psic_iar1 =0xFFFFFFFF; *psic_iar2 =0xffff5fff;//Set interrupt level parameter to 5Register_handler (Ik_ivg12, FLAGA_ISR);//Tell interrupt Manager to use interrupt level 12, interrupt flag is FLAGA_ISR*psic_imask =0x00080000;//Enable external interruptInterrupt function: Ex_interrupt_handler (FLAGA_ISR)//Set Interrupt function flag to FLAGA_ISR{if(*pfio_flag_d = = PF0)//Determine if the PF0 is interrupted{printf("Interrupt is pf0!\n");}Else if(*pfio_flag_d = = PF1)//Determine if the PF1 is interrupted{printf("Interrupt is pf1!\n");} *pfio_flag_c = pf0| PF1;//Clear Interrupt flag}

Bf53x_pll

The PLL (Phase Locked Loop) is the mechanism of the adsp-bf53x's core and clock settings, called a phase-locked loop. The current processor is configured to work through the PLL
Kernel and system clocks.

Bf53x_ebiu

Ebiu interface is adsp-bf53x external bus interface, adsp-bf53x Ebiu interface Total 16 data cable, 19 address line, support synchronization
SDRAM access and asynchronous bus peripheral access, ADSP-BF53X's asynchronous Ebiu interface has 4 banks, each bank 1MByte,
Support various bus interface devices.
#BF53x_SPI

interface function

SPI interface is a 4-wire serial port, can connect Spiflash,spi interface Ad,da and so on. The SPI interface of the ADSP-BF53X supports both host mode and slave mode, it has 7 SPI slave blades, and in host mode it can mount 7 SPI devices and boot boot in either host mode or slave mode.
1, MOSI main input from the output interface, according to the host and device mode to determine the function
2, miso from the input main output interface, according to the host and device mode to determine the function
3. SCK SPI Clock
4. SPISELX SPI Device Selection interface
5, Spiss SPI from the machine chip select interface
The SPI interface clock can be as fast as 1/4 of the system clock, and its configuration formula is:
SCK Frequency = (Peripheral clock Frequency SCLK)/(2 x Spi_baud)

Interface Register Description

1, Spi_ctl SPI Control Register, configure SPI operating mode and phase, etc.
2. SPI_FLG SPI Slave Select Register for choosing which chip control device to use
3. Spi_stat SPI Status register to get SPI current working status
4. SPI_TDBR SPI Data Transfer Register
5. SPI_RDBR SPI Data Receive register
6, Spi_shadow SPI_RDBR Shadow Register, can be used to read the data
# #例子代码分析

*pspi_baud=2;//The configuration rate is1/4System clock SPI rate = sclk/2*spi_baud*PSPI_FLG|=FLS2;//Select SPISEL2 Interface*pspi_ctl=0x1001| cpha| Cpol;//Configuration mode for manual chip selection mode*pspi_ctl= (*pspi_ctl| SPE);//Enable SPI interface*PSPI_FLG&= ~flg2;//Pull the SPISEL2 to0 while(! (*pspi_stat& Spif));//To see if the SPI transfer status is complete*PSPI_TDBR=0x55;//Transmitting data to the SPI transmit data register*PSPI_FLG|= FLG2;//Pull the SPISEL2 to1, Complete data transfer*PSPI_FLG&= ~flg2;//Pull the SPISEL2 to0 while(*pspi_stat& RXS)//view SPI transmit status whether there is data to receive i =*PSPI_RDBR;//Reading data*PSPI_FLG|= FLG2;//Pull the SPISEL2 to1, Complete data transfer

ADSP-BF53X's SPI interface supports manual chip selection and automatic chip selection in two modes, through the Cpha and Cpol bit configuration of the SPI_CTL register, the example code uses manual chip selection mode, which requires code to select and close the chip selection after each reading and data reading.

Bf53x_timer interface function

There are 3 universal timers on the adsp-bf53x, with three modes per timer:
1. Pulse width modulation mode (pwm_out)
2. Pulse Width count capture mode (WDTH_CAP)
3. External event mode (EXT_CLK)
# #接口寄存器说明
Timerx_config Timer Configuration Register to set timer operating mode
Timerx_width Timer width Register, set output waveform pulse width
Timerx_period Timer Cycle Register to set the period of the output waveform
Timerx_counter Timer count Register, read the number of pulses captured
Timer_enable Timer Enable register
timer_disable Timer off Register
Timer_status Timer Status Register

Example code Analysis

The code implements the timer configuration to pwm_out mode, timer interrupt to timing a 0x00800000 system of the length of time,
When completed, the information is printed within the interrupt.
The timer does not have a separate timing function, so if it is timed, it can use the Pwm_out mode and timer interrupt to
On the TIMER0 pin of the chip, there will be a PWM waveform output.

*ptimer0_config =0x0019;//Configure timer for PWM mode*ptimer0_period =0x00800000;//Set period is 0x00800000 system clock*ptimer0_width =0x00400000;//Set pulse width to 0x00400000 system clock*ptimer_enable =0x0001;//Enable TIMER0*PSIC_IAR0 =0xFFFFFFFF; *psic_iar1 =0xFFFFFFFF; *psic_iar2 =0xfffffff4;//Configure interrupt level data to 4Register_handler (ik_ivg11, TIMER0_ISR);//Registered interrupt level is 11, identifier is TIMER0_ISR*psic_imask =0x00010000; Ex_interrupt_handler (TIMER0_ISR)//Interrupt function with identifier TIMER0_ISR{*ptimer_status =0x0001;//Clear timer Interrupt flagprintf("Timer0 Interrupt!\n");//Print information}

Bf53x_uart Interface Function Introduction

UART (Universal asynchronous Receiver/transmitter (UART) port) interface, is a full-duplex universal serial interface, consisting of Rx and TX Two lines, the expansion of the RS232 chip can be directly and the computer serial communication, Typically used as a debug command and data communication interface.

Interface Register Description

UART_THR UART Transmit Data register
UART_RBR UART Receive Cache register
Uart_dll UART Baud rate configuration Low 8-bit register
UART_DLH UART baud rate configuration High 8-bit register
Uart_ier UART Interrupt Enable register
Uart_iir UART Interrupt Recognition Register
UART_LCR UART Line Control register
UART_MCR UART Modulation Control register
UART_LSR UART Line Status register
UART_SCR UART Staging Register
UART_GCTL UART Global Control Register
# #例子代码分析

*puart_gctl=0x0009; *puart_lcr=0x0080;//dlab=1 allow access to DLLs and DLH*puart_dll=div;//write the value of the variable div to the baud rate configuration register*puart_dlh=div>>8;//dll DLH respectively assigned value*puart_lcr=0x0003;//Allow access to RBR THR and Ier*puart_ier=0x0001;//Receive interrupt allow*PSIC_IAR0 =0xFFFFFFFF; *psic_iar1 =0xf3ffffff;//UART interrupt level setting*PSIC_IAR2 =0xFFFFFFFF; Register_handler (IK_IVG10, UART_ISR);//Registered UART Interrupt level is 10, flag is UART_ISR*psic_imask =0x00004000;//Enable UART to interrupt*puart_thr=txbuf[i];//write data to UART transmit data register while(! (*puart_lsr&0x0020));//wait for transmission to completeEx_interrupt_handler (UART_ISR)//uart receive data interrupt function{if(*PUART_LSR&DR)//To determine if there are new data. {if(Cont> +)//Prevent buff overflow, test code, repeat the received data to the 512-byte buffCont=0; rxbuf[Cont]=*PUART_RBR;//Read DataCont++;} }

The code implements a configuration baud rate of 9600, sets the data receive interrupt, after running the code, the string in the array txbuf is sent through the serial port, when the data is received, it enters the interrupt function to read the data.

Bf53x_ppi Interface Function Introduction

The PPI (Parallel peripheral Interface) interface is commonly used for the transmission of video signals and synchronous data on adsp-bf53x, and is a half-duplex interface that supports data acquisition and data transmission.
Adsp-bf533x has a 16Bit PPI interface, the highest speed can be up to 1/2 of the system clock, video signal transmission using the row, column, field is three synchronization signal, support itu656,itu601 and other modes, compatible with most video-related chips.
The PPI interface itself does not produce a clock signal, so the PPICLK signal must be provided by an external device or crystal oscillator, it does not have a dedicated line, row synchronization signal pin, in the use of PPI, with its multiplexed Timer1 and Timer2 pins to be used as row and column synchronization signal pin, PPI The field synchronization pin FS3 of the interface is multiplexed with the PF3 pin, which indicates whether the current transmitted signal is an odd or even field signal when transmitting a TV video signal, which must be pulled down in the case where it is not normally used. Unlike other interfaces, the PPI interface does not have a register for sending and receiving data, and cannot use the core to manipulate data, only DMA transmissions. PPI interface Pins and multiplexing definitions:

Interface Register Description

Ppi_control PPI Control register to configure the PPI operating mode
Ppi_status PPI Status Register
Ppi_count PPI Transfer Count register, set the image a line consists of how much data
Ppi_delay PPI delay Count Register, set how many clocks are delayed at the time of transmission to start data mining
Ppi_frame PPI Frame register, used to set the number of lines in a frame of a full image

Example code Analysis

*PDMA0_START_ADDR =0;//Configure PPIDMA data start address*pdma0_x_count =480;//Configure DMA How many times to transfer the data in a row*pdma0_x_modify =2;//configure increments for each transfer line address*pdma0_y_count =286;//Configure how many rows of data to transfer*pdma0_y_modify =2;//Configure increments for each column data address*pdma0_config =0x1034;//Configure DMA operating mode*pppi_control =0X781E;//Configure PPI work couple Yes*pppi_delay =0;//Configure clock delay of 0*pppi_count =479;//Configure PPI to transfer 480 times per line*pppi_frame =286;//Configure 286 rows per frame image*ptimer1_period =525;//Configure the cycle of line synchronization signal generation*ptimer1_width = A;//Configure line sync signal width*ptimer1_config =0X00A9;//Configure line sync signal operating mode*ptimer2_period =150150;//Configuration column synchronization signal generation cycle*ptimer2_width =5250;//Configure column sync signal width*ptimer2_config =0X00A9;//Configure column Sync signal operating mode*pdma0_config |=0X1;//Enable DMAASM("Ssync;");//System synchronization*pppi_control |=0X1;//Enable PPIASM("Ssync;");//System synchronization*ptimer_enable|=0x0006;//Enable line-field synchronization signalASM("Ssync;");//System synchronizationThe//ppi synchronization signal is multiplexed with TIMER1 and TIMER2, so configure the timer register to start the PPI sync signal. 

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BF531 Notes of DSP