Communication test between DSPs and FPGA Based on c66x Platform

This paper is a DSP and FPGA communication test based on chuanglong TL665xF-EasyEVM Development Board. The brief introduction of the TL665xF-EasyEV Development Board is as follows: consists of the core board + the bottom board.
The core board DSP end adopts single-core tms320c6655 or dual-core tms320c6657 processor, FPGA end adopts Xilinx Artix-7 processor to realize heterogeneous multi-core processor architecture, DSP and FPGA internal through UPP, emif16, SRIo connection;
The baseboard interface has rich resources and supports UPP, emif16, SRIo, Gigabit Ethernet ports, and other high-speed interfaces. The PCIe interface is introduced, and a single port is dual-channel with a maximum communication rate of 5 gbaud per channel;
SFP interface, transmission rate up to 5 Gbit/s, can be connected to SFP optical port module or SFP electrical port module;
Dual-channel xadc interface for analog-to-digital conversion and flexible configuration of logical input;
Industrial FMC interface is also introduced, supporting high-speed ADC, DAC and Video Input and Output FMC-LPC standard module;
TL665xF-EasyEVM Development Board has a wide range of applications, can be used for machine vision, software radio, radar/sonar, medical instruments, optical fiber cable census instruments, etc.

Enter the subject below:
To communicate between DSP and FPGA, you need to set the 5th-bit dial switch of the Development Board to 1 and start the Development Board in IBL nor mode.
Test Description: The DSP server loads the. Bit file required by FPGA Through the TFTP server, and runs commands on the DSP server for testing.
(1) Test Procedure
? Deploy a TFTP server
Open the TFTP server, path: "CD files/demo/hostapp/tftpd32.exe", select current directory. the path of the BIT file (not Chinese). Server interfaces selects the IP address of the computer terminal, as shown in:

? Enable network support
Run the ndkdhcp command on the serial port debugging terminal to start the network support.

? Use tfpt to load FPGA Images
Execute commands on the serial port debugging terminal to load the FPGA image. The command format is as follows:
Tronlong> fpgaprogtftp [computer terminal IP address] [FPGA image file name]
Take I2C image as an example:
Tronlong> fpgaprogtftp192.168.0.135i2c _ test. Bit
You can view the File Transfer Progress on the tftpd server. After the file transfer is complete, you can program FPGA, as shown in:

After the programming is complete, the program result is displayed, as shown in:

? Run the test command on the DSP.
Run the following command on the serial port debugging terminal to test the FPGA image:
Tronlong> fpgai2c

The following test DSP communicates with FPGA through I2C, EMIF, SRIo, and file system. FPGA images can be obtained from the FPGA-side optical disc demo.
(2) Communication test between DSP and FPGA I2C
Load the I2C Image According to the above test steps, as shown in:

(3) communication test between DSP and FPGA SRIo
Run the following command to test SRIo communication:
Tronlong> fpgaprogtftp192.168.0.135srio _ dsp_2x.bit // The actual IP address of the computer terminal shall prevail.

Tronlong> fpgasrio

(4) communication test between DSP and FPGA emif16
Run the following command to test the emif16 communication:
Tronlong> fpgaprogtftp192.168.0.135emifa _ top. Bit

Tronlong> fpgaemif

Communication test between DSPs and FPGA Based on c66x Platform