DSP 28335 Interrupt System Summary--Source: Li Xuri _ Chick Electronics

Pie is connected to 12 broken lines in the 28335 cores via 12 wires. and the other pie

One side has a 12*8 root line connected to peripherals, such as AD, SPI, Exint, and so on. This allows the pie to manage 12*8=96 external interrupts altogether. These 12 sets of large interrupts are controlled by the 28335-core interrupt register ier.

The IER determines which group of interrupts each interrupt belongs to (such as Ier |= m_int12; we're going to use the 12th set of interrupts, but what's in the 12th group does not know what interrupts the CPU

To be determined again by Pieier). Next, the lower 8 in the register Pieier in the pie module determines that the interrupt is the first interrupt of this group, which is told to the CPU (we are not

Like to Pieier Total 12 is always from Pieier1-pieier12). In addition, the pie module also has the interrupt flag register PIEIFR, and its low 8 bits are 8 flag bits from the external interrupt, with

The IFR register of the sample CPU is the flag register of the interrupt group. As a result, all interrupt registers of the CPU control 12 sets of interrupts, and all the interrupt registers of PIE control 8 interrupts within each group.

In addition, we use which external interrupt, corresponding to the external interrupt register, it should be noted that the external interrupt flag to be cleared by the software itself. And the pie and CPU

The interrupt flag register is zeroed by the hardware.

is the specific meaning of intx.y.

External interrupt Source

summarized as: External interrupt1and the2 and a Xnmi .only toGPIO0-GPIO31configuration, external interrupt3and the4,5,6,7only toGPIO32-GPIO63configuration.

User interrupts are divided into three parts: peripheral level, pie level, CPU level

The three-stage series constitutes an interruption.

1. Peripheral Level Interrupt --interrupt flag must be removed by software

2.pie interrupts can support 96 separate interrupts, broken down into 8 groups, each with 12 interrupts.

The CPU takes 9 clock cycles to get the interrupt vector address and holds the critical register data before the interrupt program can be executed.

28335 supports a non-shielded interrupt (NMI) and 16 unshielded interrupts (Int1-int14,rtosint,dlogint) at the CPU level.

Pie module brings together 8 peripheral and pin interrupts into one CPU interrupt

PIE group1----GROUP12 respectively for CPU Interrupt 1---interrupt 12

For non-shielded interrupts, it goes directly to the CPU level.

For masked interrupts, the pie module has associated flag registers (PIEIFRX and Pieierx) (x=1-------12) with each bit set to Y (Y=1-----8)

Pieierx.y and Pieifrx.y,

In addition, for each pie interrupt group (1----12) There is also a pie response flag bit pieack, such as Pieackx (x=1----12)

The mechanism is as follows: when there is an interrupt request to enter the pie controller, the relevant PIE interrupt flag bit pieifrx.y high. If the pie interrupt allows the bit pieierx.y to also be set high, the PIE controller has the opportunity to check the PIEACKX flag bit to determine if the CPU is ready to receive the interrupt for this pie interrupt group.

If the pieackzx is zeroed, PIE will send the interrupt request to the CPU level.

If the Pieackx position is one, then pie waits until the flag is cleared 0 and then sends an interrupt request to the CPU-level intx. (tms320f2833x SYSTEM CONTROL and interrupts REFERENCE guide)

Pie Interrupt Register: PIECTRL,PIEACK,PIEIFRX

3 CPU-level interrupts

Once the interrupt request reaches the CPU level, the CPU level and the INTX corresponding interrupt flag bit (IFR) is set one, if the CPU interrupt allow register (IER) or debug interrupt allow register (dbgier) and the global interrupt screen bit (INTM) is allowed, the CPU will execute the interrupt request.

Registers that require manual zeroing during interrupts:Pieackx Write 1 Clear 0

CPU Interrupt Register: IFR,IER,XINTNCR external Interrupt control register (xint1~xint7,n=1~7 support). XINT13 and non-shielded interrupt Xnmi multiplexing), XNMICR external NMI Interrupt control register

Timer for the general controller and DSP chip is a basic peripheral, C2000 series of DSP timer operation method is basically similar to 28335 of the timer 0 For example, said its use.

Timer 0 using (1) should first turn on the timer's clock enable SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; CPU Timer 0 (2) adds the peripheral interrupt handle (a) to the main program to interrupt the TCR register (b) ier|=m_int1, the INT1 interrupt to enable the connection, and (c) piectrlregs.pieier1.bit.intx7=1; Enable the 7th interrupt in the tint0,1 Group, (3) Initialize the clock: including the initialization of the TIMER0 timer point to the corresponding address, the timing period setting, Timer clock configuration, timer divider setting, can be summarized as initcputimers (), (4) configuration Timer0, i.e. Configcputimer (&CPUTIMER0, 150, 500000), (5) Open interrupt Eint;ertm; (6) Open timer: cputimer0regs.tcr.bit.tss=0; (7) The interrupt response function needs: PieCtrlRegs.PIEACK.all = Pieack_group1;

Here is an example of an external interrupt, outside a button to the GPIO15 input as an external interrupt source, each time you click the button to trigger an interrupt, count+1 in the ISR.

title:dsp2833x External Interrupt test program.

//

//

Xint1 input is synched to Sysclkout

//

Watch Variables:

Xint1count for the number of times through XINT1 interrupt

Loopcount for the number of times through the idle loop

//

#include "dsp28x_project.h"//Device Headerfile and Examples include File

Prototype statements for functions found within this file.

interrupt void Xint1_isr (void);

Global variables for this example

Volatile Uint32 Xint1count;

Uint32 Loopcount;

#define DELAY 35.700L

void Main (void)

{

Step 1. Initialize System Control:

PLL, WatchDog, enable peripheral clocks

This example function was found in the Dsp2833x_sysctrl.c file.

Initsysctrl ();

Step 2. Initalize GPIO:

This example function was found in the dsp2833x_gpio.c file and

Illustrates how to set the GPIO to it's default state.

Initgpio (); Skipped for this example

Step 3. Clear all interrupts and initialize PIE vector table:

Disable CPU Interrupts

DINT;

Initialize PIE Control registers to their the default state.

The default state was all PIE interrupts disabled and flags

is cleared.

This function was found in the Dsp2833x_piectrl.c file.

Initpiectrl ();

Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;

Initialize the PIE vector table with pointers to the shell Interrupt

Service Routines (ISR).

This would populate the entire table, even if the interrupt

Is isn't used in this example. This is the useful for debug purposes.

The shell ISR routines is found in dsp2833x_defaultisr.c.

This function was found in dsp2833x_pievect.c.

Initpievecttable ();

Interrupts that is used in this example is re-mapped to

ISR functions found within this file.

Eallow; This is needed to write to Eallow protected registers

Pievecttable.xint1 = &xint1_isr;

EDIS; This is needed to disable write to Eallow protected registers

Step 4. Initialize all the Device peripherals:

This function was found in DSP2833X_INITPERIPHERALS.C

Initperipherals (); Not required for this example

Step 5. User specific code, enable interrupts:

Clear the Counters

Xint1count = 0; Count Xint1 Interrupts

Loopcount = 0; Count Times through Idle loop

Enable Xint1 and XINT2 in the Pie:group 1 Interrupt 4 & 5

Enable Int1 which is connected to Wakeint:

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; Enable the PIE block

PieCtrlRegs.PIEIER1.bit.INTx4 = 1; Enable PIE gropu 1 INT4 XINT1

IER |= m_int1; Enable CPU Int1

Eint; Enable Global Interrupts

GPIO0 is inputs

Eallow;

GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; Gpio 15 as Gpio, on button

GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; Input as Inputs

GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0;//Xint1 Synch to sysclkout only, search for Gpaqsel keywords in pdf

EDIS;

GPIO15 is XINT1

Eallow;

GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 15; Xint1 is GPIO0 modifying GPIO15 GPIO 15 as external interrupt 1

EDIS;

Configure XINT1

XIntruptRegs.XINT1CR.bit.POLARITY = 0; Falling edge interrupt falling edge trigger

Enable XINT1

XIntruptRegs.XINT1CR.bit.ENABLE = 1; Enable Xint1

Step 6. IDLE Loop:

for (;;)

{

}

}

Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:

If local ISRs is used, reassign vector addresses in vector table as

Shown in Step 5

interrupt void Xint1_isr (void)

{

GpioDataRegs.GPBCLEAR.all = 0x4; GPIO34 is low

xint1count++;

Acknowledge this interrupt to get more from Group 1

PieCtrlRegs.PIEACK.all = Pieack_group1; 0X0001, first set of ACK write 1 zeroing

}

Tags:DSP interrupt Timer 28335

Category: Dsp

Pie is connected to 12 broken lines in the 28335 cores via 12 wires. and the other pie

One side has a 12*8 root line connected to peripherals, such as AD, SPI, Exint, and so on. This allows the pie to manage 12*8=96 external interrupts altogether. These 12 sets of large interrupts are controlled by the 28335-core interrupt register ier.

The IER determines which group of interrupts each interrupt belongs to (such as Ier |= m_int12; we're going to use the 12th set of interrupts, but what's in the 12th group does not know what interrupts the CPU

To be determined again by Pieier). Next, the lower 8 in the register Pieier in the pie module determines that the interrupt is the first interrupt of this group, which is told to the CPU (we are not

Like to Pieier Total 12 is always from Pieier1-pieier12). In addition, the pie module also has the interrupt flag register PIEIFR, and its low 8 bits are 8 flag bits from the external interrupt, with

The IFR register of the sample CPU is the flag register of the interrupt group. As a result, all interrupt registers of the CPU control 12 sets of interrupts, and all the interrupt registers of PIE control 8 interrupts within each group.

In addition, we use which external interrupt, corresponding to the external interrupt register, it should be noted that the external interrupt flag to be cleared by the software itself. And the pie and CPU

The interrupt flag register is zeroed by the hardware.

is the specific meaning of intx.y.

External interrupt Source

summarized as: External interrupt1and the2 and a Xnmi .only toGPIO0-GPIO31configuration, external interrupt3and the4,5,6,7only toGPIO32-GPIO63configuration.

User interrupts are divided into three parts: peripheral level, pie level, CPU level

The three-stage series constitutes an interruption.

1. Peripheral Level Interrupt --interrupt flag must be removed by software

2.pie interrupts can support 96 separate interrupts, broken down into 8 groups, each with 12 interrupts.

The CPU takes 9 clock cycles to get the interrupt vector address and holds the critical register data before the interrupt program can be executed.

28335 supports a non-shielded interrupt (NMI) and 16 unshielded interrupts (Int1-int14,rtosint,dlogint) at the CPU level.

Pie module brings together 8 peripheral and pin interrupts into one CPU interrupt

PIE group1----GROUP12 respectively for CPU Interrupt 1---interrupt 12

For non-shielded interrupts, it goes directly to the CPU level.

For masked interrupts, the pie module has associated flag registers (PIEIFRX and Pieierx) (x=1-------12) with each bit set to Y (Y=1-----8)

Pieierx.y and Pieifrx.y,

In addition, for each pie interrupt group (1----12) There is also a pie response flag bit pieack, such as Pieackx (x=1----12)

The mechanism is as follows: when there is an interrupt request to enter the pie controller, the relevant PIE interrupt flag bit pieifrx.y high. If the pie interrupt allows the bit pieierx.y to also be set high, the PIE controller has the opportunity to check the PIEACKX flag bit to determine if the CPU is ready to receive the interrupt for this pie interrupt group.

If the pieackzx is zeroed, PIE will send the interrupt request to the CPU level.

If the Pieackx position is one, then pie waits until the flag is cleared 0 and then sends an interrupt request to the CPU-level intx. (tms320f2833x SYSTEM CONTROL and interrupts REFERENCE guide)

Pie Interrupt Register: PIECTRL,PIEACK,PIEIFRX

3 CPU-level interrupts

Once the interrupt request reaches the CPU level, the CPU level and the INTX corresponding interrupt flag bit (IFR) is set one, if the CPU interrupt allow register (IER) or debug interrupt allow register (dbgier) and the global interrupt screen bit (INTM) is allowed, the CPU will execute the interrupt request.

Registers that require manual zeroing during interrupts:Pieackx Write 1 Clear 0

CPU Interrupt Register: IFR,IER,XINTNCR external Interrupt control register (xint1~xint7,n=1~7 support). XINT13 and non-shielded interrupt Xnmi multiplexing), XNMICR external NMI Interrupt control register

Timer for the general controller and DSP chip is a basic peripheral, C2000 series of DSP timer operation method is basically similar to 28335 of the timer 0 For example, said its use.

Timer 0 using (1) should first turn on the timer's clock enable SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; CPU Timer 0 (2) adds the peripheral interrupt handle (a) to the main program to interrupt the TCR register (b) ier|=m_int1, the INT1 interrupt to enable the connection, and (c) piectrlregs.pieier1.bit.intx7=1; Enable the 7th interrupt in the tint0,1 Group, (3) Initialize the clock: including the initialization of the TIMER0 timer point to the corresponding address, the timing period setting, Timer clock configuration, timer divider setting, can be summarized as initcputimers (), (4) configuration Timer0, i.e. Configcputimer (&CPUTIMER0, 150, 500000), (5) Open interrupt Eint;ertm; (6) Open timer: cputimer0regs.tcr.bit.tss=0; (7) The interrupt response function needs: PieCtrlRegs.PIEACK.all = Pieack_group1;

Here is an example of an external interrupt, outside a button to the GPIO15 input as an external interrupt source, each time you click the button to trigger an interrupt, count+1 in the ISR.

title:dsp2833x External Interrupt test program.

//

//

Xint1 input is synched to Sysclkout

//

Watch Variables:

Xint1count for the number of times through XINT1 interrupt

Loopcount for the number of times through the idle loop

//

#include "dsp28x_project.h"//Device Headerfile and Examples include File

Prototype statements for functions found within this file.

interrupt void Xint1_isr (void);

Global variables for this example

Volatile Uint32 Xint1count;

Uint32 Loopcount;

#define DELAY 35.700L

void Main (void)

{

Step 1. Initialize System Control:

PLL, WatchDog, enable peripheral clocks

This example function was found in the Dsp2833x_sysctrl.c file.

Initsysctrl ();

Step 2. Initalize GPIO:

This example function was found in the dsp2833x_gpio.c file and

Illustrates how to set the GPIO to it's default state.

Initgpio (); Skipped for this example

Step 3. Clear all interrupts and initialize PIE vector table:

Disable CPU Interrupts

DINT;

Initialize PIE Control registers to their the default state.

The default state was all PIE interrupts disabled and flags

is cleared.

This function was found in the Dsp2833x_piectrl.c file.

Initpiectrl ();

Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;

Initialize the PIE vector table with pointers to the shell Interrupt

Service Routines (ISR).

This would populate the entire table, even if the interrupt

Is isn't used in this example. This is the useful for debug purposes.

The shell ISR routines is found in dsp2833x_defaultisr.c.

This function was found in dsp2833x_pievect.c.

Initpievecttable ();

Interrupts that is used in this example is re-mapped to

ISR functions found within this file.

Eallow; This is needed to write to Eallow protected registers

Pievecttable.xint1 = &xint1_isr;

EDIS; This is needed to disable write to Eallow protected registers

Step 4. Initialize all the Device peripherals:

This function was found in DSP2833X_INITPERIPHERALS.C

Initperipherals (); Not required for this example

Step 5. User specific code, enable interrupts:

Clear the Counters

Xint1count = 0; Count Xint1 Interrupts

Loopcount = 0; Count Times through Idle loop

Enable Xint1 and XINT2 in the Pie:group 1 Interrupt 4 & 5

Enable Int1 which is connected to Wakeint:

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; Enable the PIE block

PieCtrlRegs.PIEIER1.bit.INTx4 = 1; Enable PIE gropu 1 INT4 XINT1

IER |= m_int1; Enable CPU Int1

Eint; Enable Global Interrupts

GPIO0 is inputs

Eallow;

GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; Gpio 15 as Gpio, on button

GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; Input as Inputs

GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0;//Xint1 Synch to sysclkout only, search for Gpaqsel keywords in pdf

EDIS;

GPIO15 is XINT1

Eallow;

GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 15; Xint1 is GPIO0 modifying GPIO15 GPIO 15 as external interrupt 1

EDIS;

Configure XINT1

XIntruptRegs.XINT1CR.bit.POLARITY = 0; Falling edge interrupt falling edge trigger

Enable XINT1

XIntruptRegs.XINT1CR.bit.ENABLE = 1; Enable Xint1

Step 6. IDLE Loop:

for (;;)

{

}

}

Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:

If local ISRs is used, reassign vector addresses in vector table as

Shown in Step 5

interrupt void Xint1_isr (void)

{

GpioDataRegs.GPBCLEAR.all = 0x4; GPIO34 is low

xint1count++;

Acknowledge this interrupt to get more from Group 1

PieCtrlRegs.PIEACK.all = Pieack_group1; 0X0001, first set of ACK write 1 zeroing

}

DSP 28335 Interrupt System Summary--Source: Li Xuri _ Chick Electronics