Electric Game Summary (ii)--AD chip summary of the AD7715

First, the characteristic parameter

1, 16-bit non-distorted ad converter

2, Gain adjustable, can be switched in 1,2,32,128.

3, digital and analog to separate, can reduce noise.

4, with a large output current, has a better carrying capacity.

Second, the pin arrangement

Three, pin function

Pin Name	Function
SCLK	Serial clock, Schmitt logic input. Add an external serial clock to this input port to access the AD7715 serial data. Control clocks when transmitting data to and from a single chip microcomputer
Mclkin	Provides a master clock signal for the converter. Can be supplied in the form of a crystal/resonator or an external clock. The crystals/resonators can be connected between the Mclkin and the Mclkout two pins. In addition, the Mclkin is also available with CMOS-compatible clock drivers, while the mclkout is not connected. The clock frequency range is 500khz~5mhz
Mclkout	When the main clock is a crystal/resonator, the crystal/resonator is connected between the Mclkin and the mclkout. If an external clock is connected at the Mclkin pin, the mclkout will provide an inverting clock signal. This clock can be used to provide a clock source for an external circuit and can drive a CMOS load. If the user does not need it, the mclkout can be switched off via the Clkdis bit in the clock register. This way, the device does not drive the capacitive load on the mclkout foot and consumes unnecessary power
CS '	Chip selection, low-level active logic input, select AD7715. The PIN is connected to a low level, and the AD7715 can operate in a three-wire interface mode (SCLK, DIN, and Dout interface with the device). In systems with multiple devices on the serial bus, the CS ' Choice can be made for these devices, or CS ' may be used as a frame sync signal when communicating with the AD7715
RESET	Reset the input. Low-active input to reset the device's control logic, interface logic, calibration coefficients, digital filters, and analog modulators to the power state
AVDD	Analog supply voltage, 5V
AVIN (+)	Positive inputs for differential analog inputs
AVIN (-)	Negative inputs for differential analog inputs
REFIN (+)	The reference input is differential and specifies that Refin (+) must be greater than Refin (-). REFIN (+) can take any value between VDD and GND
REFIN (-)	The reference input, REFIN (-) can take any value between VDD and GND, and satisfies REFIN (+) greater than REFIN (-)
AGND	Simulated ground
DRDY '	Logical output. The logic low on this output indicates that a new output word can be obtained from the ad7705/7706 data register. Once the read operation for a full output word is completed, the DRDY ' pin immediately returns to the high level. If data readout does not occur between two output updates, DRDY ' will return high at 500xtCLKIN time before the next output update. When Drdy ' is at high level, it cannot be read, so that the data in the data register is not read when it is being updated. When the data is updated, DRDY ' will return to the low level. DRDY ' is also used to indicate when ad7705/7706 has completed the on-chip calibration sequence.
DOUT	Serial Data Output terminal
Din	Serial data input terminal
DVDD	Digital supply voltage, can be 3.3V
DGND	Digitally to

Iv. in-chip register 1, overview

There are only four registers, namely communication, settings, data and calibration registers. Generally only use communication and settings as well as data registers. And each time the operation is to operate the communication register, and then skip to the selected next register to read and write.

2. Communication Register

Pin Name	Function
0/drdy '	This means that "0" must be written, otherwise the operation of the Register cannot proceed.
ZERO	This one must write "0", otherwise the chip may not work properly.
Rs1–rs0	Select the next register for communication
STBY	"1" means to enter the low power mode, the power consumption is only 10uW, "0" is normal operation, the general default is "0".
G1-g0	Setting the Gain multiplier

3. Set the Register

Pin Name	Function
MD1 MD0
Class	Clock bit. The CLK bit should be set according to the operating frequency of the ad7705/7706. If the converter has a primary clock frequency of 2.4576MHz (clkdiv=0) or 4.9152MHz (clkdiv=1), CLK should be "0". If the device has a primary clock frequency of 1MHz (clkdiv=0) or 2MHz (clkdiv=1), the bit should be "1". This bit sets the appropriate scale current for a given operating frequency, and also (along with FS1 and FS0) selects the output update rate of the device.
FS1, FS0	The filter select bit, which together with CLK determines the output update rate of the device. Table 12 shows the first notch and -3db frequency of the filter.
B/u '	"0" indicates bipolar setting "1" indicates unipolar setting
BUF	"1" means two-way, "0" means no crossover
FSYNC	Filter synchronization. At high level, the Digital filter node, filter control logic and calibration control logic are in the reset state, while the analog modulator is also controlled in the reset state. When at low level, the modulator and the filter begin to process the data and produce a valid word within the 3x (1/output update rate) time (i.e. the filter's settling time). The FSYNC does not affect the digital interface and does not reset the Drdy ' output (if it is low).

4. Data register

The data register is a 16-bit read-only register that contains the latest conversion results from AD7715. If the communication register sets the device to write to the register, it is bound to actually have a write operation to return the device to the write operation for the communication register, but the 16-bit number written to the device will be AD7715 ignored.

Five, chip peripheral circuit diagram

VI. Stm32f103zet driver (in IO port emulation mode)

#ifndef __adc7715_h#define__adc7715_h#include"stm32f10x.h"#include"pbdata.h"#include"spi.h"//self-coding functions#include"Timer.h"#include"gpio.h"#include"baseFunc.h"#defineSCLK Pin0#defineDIN Pin1#defineDOUT Pin2#defineDRDY Pin3voidwritead7715data (U8 data);voidDelay_ms (intTime ); U32 readad7715data (U8byte);voidInitAD7715 (void); u32 Getad7715num (void);#endif

#include"adc7715.h"voidDelay_ms (intTime )    {u32 i,j;  for(i=time;i>0; i--)    {         for(j=0;j< +; j + +)        {                    }    }}voidwritead7715data (U8 data) {U8 I;  for(i=0;i<8; i++)    {        if((data&0x80)!=0) {Set_outh (Gpioa,din); }        Else{set_outl (Gpioa,din); } Data=data<<1; Delay_ms (Ten);        Set_outh (GPIOA,SCLK); Delay_ms (Ten);        Set_outl (GPIOA,SCLK); Delay_ms (Ten);        Set_outh (GPIOA,SCLK); Delay_ms (Ten);    } set_outh (Gpioa,din); Delay_ms (Ten);} U32 Readad7715data (U8byte) {U8 i; U32 Data=0;  for(i=0;i<byte*8; i++) {Set_outh (GPIOA,SCLK); Delay_ms (Ten);        Set_outl (GPIOA,SCLK); Delay_ms ( -); Data=data<<1; if(read_in (gpioa,dout) = =1) {Data=data+1;      } set_outh (GPIOA,SCLK); Delay_ms (Ten); }    returndata;}voidInitAD7715 (void) {set_out (GPIOA,SCLK|DIN); Set_fin (Gpioa,dout|DRDY); Writead7715data (0x10); Writead7715data (0x66); }u32 Getad7715num (void){     while(read_in (gpioa,drdy) = =1); Writead7715data (0x38); returnReadad7715data (2);}

Electric Game Summary (ii)--AD chip summary of the AD7715