High-Speed PCB design knowledge Q &

Expert answers to high-speed line cabling questions 1
1. How to deal with some theoretical conflicts in actual cabling
Q: In actual cabling, many theories conflict with each other;
Example: 1. The connection method for processing multiple models/Data locations: In theory, it should be isolated from each other, but in practical miniaturization and high-density wiring, due to space limitations or absolute isolation, it may lead to too long line routing for small signal simulation, and it is difficult to implement the theoretical method. My practice is: divide the module of the module into a complete isolated island. The module of the module is connected to the isolated island of the module. Connect the island to the "big" area through the channel. I wonder if this approach is correct?
2. Theoretically, the line between the crystal oscillator and the CPU should be as short as possible. Due to the structural layout, the line between the crystal oscillator and the CPU is long and thin, so it is disturbed and unstable, how can we solve this problem from cabling? There are still many such problems, especially the EMC and EMI Problems in High-Speed PCB wiring. There are many conflicts and they are a headache. How can we solve these conflicts?

Answer: 1. Basically, it is right to divide and isolate the modulus/number. It should be noted that the signal line should not be crossed through a separate place (moat), or the returning current path of the power supply and signal should be too large.
2. the crystal oscillator is a simulated positive feedback oscillator circuit. to have stable oscillating signals, the loop gain and phase specifications must be met, and the oscillation specifications of the analog signals are easily disturbed, even if ground guard traces is added, interference cannot be completely isolated. If it is too far away, the noise on the ground plane will also affect the positive feedback oscillator circuit. Therefore, you must keep the crystal oscillator close to the chip.
3. There are indeed many conflicts between high-speed cabling and EMI requirements. However, the basic principle is that the electrical characteristics of the signal cannot be non-compliant due to the Resistance Capacitance or Ferrite Bead added by EMI. Therefore, it is best to solve or reduce EMI problems by arranging cabling and PCB laminated techniques, such as high-speed signal passing through the inner layer. At last, the resistance and capacitance or Ferrite Bead method is used to reduce the damage to the signal.

2. In high-speed design, how can we solve the problem of signal integrity? How is differential cabling implemented? How to implement differential cabling for clock signal lines with only one output end?
A: signal integrity is basically a problem of impedance matching. Factors that affect impedance matching include the signal source architecture and output impedance (output impedance), the characteristic impedance of the line, the characteristics of the load end, And the topology architecture. The solution is to rely on termination and adjust the topology of the cabling. There are two points for differential cabling. One is that the length of the two lines should be as long as possible, and the other is the distance between the two lines (determined by the difference impedance) should remain unchanged, that is, to maintain parallelism. There are two parallel methods: one is to walk two lines in the same side-by-side layer, and the other is to walk two lines in the upper and lower adjacent two layers (over-under ). In general, there are many ways to implement side-by-side. The difference wiring must be the signal source and the receiver are also the difference signal to make sense. Therefore, differential cabling cannot be used for clock signals with only one output end.

Expert answers to high-speed line cabling questions 2
3. About High-speed differential signal cabling
Q: When the PCB is close to the parallel direction of the high-speed differential signal line, the impedance matching will bring many benefits due to the coupling of the two lines. However, it is suggested that this will increase the signal attenuation and affect the transmission distance. So, why? On the Evaluation boards of some large companies, I can see that some high-speed cabling systems are as close and parallel as possible, while some intentionally make the distance between the two lines suddenly and suddenly. I don't know that this kind of effect is better. My signal is above 1 GHz and the impedance is 50 ohm. In software computing, is the differential line pair also calculated in 50 ohm mode? Or 100 ohm? Can I add a matching resistance between the differential line pairs at the receiving end?
Answer: one cause of high-frequency signal energy attenuation is the electrical resistance of the conductor, including skin effect, and Dielectric Loss of the dielectric. When the two factors analyze the transmission line effect (Transmission Line effect) in electromagnetic theory, we can see the extent of their influence on signal attenuation. The coupling of the differential line will affect the Characteristic Impedance of each other, and the variation is small. According to the principle of partial pressure (Voltage Divider), this will reduce the voltage of the signal source to the online. As for the Theoretical Analysis of Signal Attenuation Caused by coupling, I have not read it, so I cannot comment on it. The wiring method of the differential pair should be properly near and parallel. The so-called proper closeness is because the spacing affects the value of the differential impedance (differential impedance), which is an important parameter for the design of the difference pair. Parallelism is also required because the consistency of the differential impedance must be maintained. If the two lines are suddenly far and near, the differential impedance will be inconsistent, which will affect the signal integrity and time delay (timing delay ). The difference impedance is calculated as 2 (z11-z12). z11 is the characteristic impedance of the cabling itself, and z12 is the impedance produced by coupling between the two differential wires, which is related to the linedistance. Therefore, to design a differential impedance of 100 ohm, the characteristic impedance of the wire itself must be slightly greater than 50 ohm. The simulation software can be used to calculate the size.

4. Q: To improve the anti-interference performance, in addition to separating analog and digital data, we only need to connect the power source with a single point. In addition, we hope that experts will give you some good suggestions and suggestions!
A: In addition to separate the ground, you should also pay attention to the power supply of the analog circuit. If the power supply is shared with the digital circuit, it is best to add a filter line. In addition, do not interlace digital and analog signals, especially do not cross the moat ).

5. Copper Grounding in blank areas of signal layer in High-Speed PCB design
Q: In the high-speed PCB design, copper can be applied to the blank area of the signal layer, so the copper applied to multiple signal layers is grounded or half grounded, how about half power supply?
A: copper is usually grounded in the vast majority of cases in the blank area. Only pay attention to the distance between copper and the signal line when applying copper next to the high-speed signal line, because the copper will reduce the Characteristic Impedance of a little wire. Do not affect the characteristic impedance of the layer, for example, in the dual stripline structure.

6. High-speed signal line Matching
Q: Why do high-speed signal lines (such as CPU data and address signal lines) need to be matched in layour, a high-speed Board (such as a P4 motherboard? What are the risks of non-matching? The matching length range (the time delay difference of the signal line) is determined by what factors, and how to calculate it?
Answer: the main reason for requiring line-Breaking Characteristic Impedance Matching is to avoid the impact of reflection on signal integrity caused by transmission line effect) and latency (flight time ). That is to say, if the signal does not match, the signal will be reflected to affect its quality. The length range of all cabling is specified according to the timing requirement. There are many factors that affect the Signal Delay Time, and the line length is only one of them. P4 requires that the length of certain signal lines be in a certain range, which is the timing margin calculated based on the transmission mode used by the signal (common clock or source synchronous, assign a part to the allowable error of the line length. As for the computing of the time series of the above two modes, it is not convenient to detail the time and length here, download "Intel Pentium 4 processor in the 423-pin package/Intel 850 chipset Platform Design Guide" from the http://developer.intel.com/design/Pentium4/guides at the following URLs ". The "methodology for determining topology and routing Guideline" section describes in detail.

7. Q: Can a test point automatically generated by software on a high-density Printed Board meet the requirements of mass production? Will adding a test point affect the quality of high-speed signals?
A: Generally, whether the software automatically generates a test point meets the test requirements depends on whether the specifications for the test points meet the requirements of the testing machines. In addition, if the cabling is too tight and the rules for adding test points are strict, there may be no way to automatically add test points to each line. Of course, you need to manually complete the test areas. As to whether the signal quality will be affected, it depends on the method of adding a test point and how fast the signal is. Basically, external testing points (via or dip PIN not existing online) may be added online or pulled from the online for a short line. The former is equivalent to adding a small capacitor online, while the latter is a branch. These two situations will have a slight impact on high-speed signals. The extent of the impact is related to the signal frequency speed and edge rate. The impact size can be learned through simulation. In principle, the smaller the test point, the better (of course, to meet the requirements of the test tool), the shorter the branch, the better.

8. How to choose a PCB Board? How can we avoid high-speed data transmission's high-frequency interference to the simulation of small signals? Are there some basic design ideas? Thank you.
A: When selecting a PCB Board, you must strike a balance between meeting the design requirements, mass production and costs. The design requirements include the electrical and institutional components. This material problem is usually important when designing very high-speed PCB boards (more than GHz frequency. For example, the commonly used FR-4 material, in the frequency of several GHz medium loss dielectric loss will have a great impact on signal attenuation, may not be used. For Electrical purposes, pay attention to whether dielectric constant and dielectric loss are used at the designed frequency. The basic idea to avoid high-frequency interference is to minimize the interference of high-frequency electromagnetic fields, that is, crosstalk ). The distance between the high-speed signal and the analog signal can be extended, or the ground guard/shunt traces can be added next to the analog signal. Pay attention to the digital noise interference to the simulated area.

9. As we all know, PCB consists of many layers, but I am not very clear about the meanings of some layers. The layers of mechanical, keepoutlayer, topoverlay, bottomoverlay, toppaste, bottompaste, topsolder, bottomsolder, drillguide, drilldrawing, and multilayer do not know their exact meaning. Please advise.
A: Many of the terms of EDA software do not have the same definition. The following is a literal explanation.
Mechnical
Keepoutlayer: defines the areas where a part cannot be laid, punched out (VIA), or placed. These restrictions can be defined separately. Topoverlay: it cannot be understood literally. Provide more information for further discussion.
Bottomoverlay: it cannot be understood literally. You can provide more information for further discussion.
Toppaste: The top layer must expose the parts of the solder paste on the copper skin.
Bottompaste: the bottom layer must expose the parts of the solder paste on the copper skin.
Topsolder: top-layer Solder Mask to avoid transient bottomsolder which may be accidentally repaired during manufacturing or in the future.
Drillguide: A table with different aperture sizes, corresponding symbols, and numbers.
Drilldrawing: refers to the bitmap of a hole. Each aperture has a corresponding symbol.
Multilayer: there should be no single layer, which can be a multi-layer panel. For single panel and double panel.

10. A system is often divided into several PCB, including power supply, interfaces, and boards. The ground wires of each Board are often interconnected, resulting in many loops, such as low-frequency loop noise, I don't know how to solve this problem?
A: When the signal or power supply between each PCB Board is in the action, for example, the board has a power supply or a signal sent to the B board, there must be an equal amount of current flowing back from the formation to the sub-board (this is Kirchoff current law ). The current in the formation flows back to the location with the smallest impedance. Therefore, the number of pins allocated to the formation cannot be too small at each interface, regardless of the power supply or signal connection, to reduce the impedance, which can reduce the noise on the formation. In addition, you can also analyze the entire current loop, especially the large part of the current, and adjust the formation or ground line method to control the current routing (for example, creating a low impedance somewhere, to reduce the impact on other sensitive signals.
11. (1) Can we provide some empirical data, formulas, and methods to estimate the impedance of the wiring. (2) When the requirements for impedance matching cannot be met, it is better to add a parallel matching resistance at the end of the signal line or a series matching resistance on the signal line. (3) Whether the ground can be added in the middle of the differential signal line
Answer: 1. two characteristic impedance formulas are provided below:. microstrip z = {87/[SQRT (ER + 1.41)]} ln [5.98 H/(0.8 w + t)] where W is the line width, T is the copper thickness of the wire, H is the distance from the wire to the reference plane, and er is the dielectric constant (dielectric constant) of the PCB ). This formula can be used only when 0.1 <(W/H) <2.0 and 1 <(ER) <15. B. stripline z = [60/SQRT (ER)] ln {4 h/[0.67 π (t + 0.8 w)]} Where H is the distance between the two reference planes, and the cabling is located in the middle of the two reference planes. This formula can be used only when W/H <0.35 and T/h <0.25. It is better to use simulation software to calculate accurately.
2. There are several factors to consider when selecting the termination method: A. source driver architecture and strength. B. The size of power consumption. C. The impact on the time delay is the most important consideration. Therefore, it is hard to say which method is better.
3. The ground line is not allowed in the middle of the differential signal. The most important aspect of differential signal application is the advantages of coupling between differential signals, such as flux cancellation and noise immunity. If a ground wire is added in the middle, the coupling effect is damaged.

12. Can you introduce some foreign books and materials on high-speed PCB design, processing capability, processing level, processing material, and related technologies?
A: currently, high-speed digital circuits are used in communication networks, computers, and other related fields. In terms of communication networks, the PCB operating frequency has reached GHz, and I know as many as 40 layers. Computer-related applications also rely on advances in chips. The maximum operating frequency on a PC or server has reached 400 MHz (such as Rambus. In response to this high-speed and high-density cabling demand, the demand for blind tracking (blind/Buried Vias), mircrovias and build-up processes is also growing. All of these design requirements can be produced by manufacturers in large quantities. The following are some good technical books: 1. Howard W. Johnson, "high-speed digital design-a handbook of black magic ";
2. Stephen H. Hall, "high-speed digital system design ";
3. Brian Yang, "digital signal integrity ";

13. design and processing of Flexible Circuit Boards
Our company plans to use flexible circuit board design to solve the problem of signal transfer and circuit board interconnectivity in small imaging systems. Does the rigid-flexible board design require special design software and specifications? In addition, where can I process such circuit boards in China?
Answer: you can design a flexible circuit board (Flexible Printed Circuit) with General PCB design software ). The same format is provided to FPC manufacturers in Gerber format. Since the manufacturing process is different from the general PCB, the manufacturers will have limits on the minimum width, minimum line distance, and the minimum aperture (VIA) based on their manufacturing capabilities. In addition, some copper at the turning point of the flexible circuit board can be reinforced. Production vendors can access the "FPC" on the Internet, which can be found in keyword queries.
14. PCB wiring Adjustment
I would like to ask a question: it takes time to adjust the machine due to the unsatisfactory machine layout. I usually use manual cabling. Most of the PCB boards I work on now use SMD chips with high pin density, and use bus (ABUS, Baidu, cbus, etc ), due to high operating frequency, the lead should be as short as possible. naturally, a very dense signal line is uniformly distributed on a small area board. I now feel that it takes a lot of time to adjust these dense signal lines. One is to adjust the distance between lines to make them as even as possible. In the Cabling Process, the cables are usually changed from time to time. For each change, the distance between each laid line must be evenly adjusted. The more it goes to the end, the more it will be. The second is to adjust the width of the line so that it can accommodate the newly added line as much as possible within a certain width. Generally, there is a lot of bending on an online line, and one bend is a piece. manual adjustment can only be made for a period of time, which also takes time. I think that, in the Cabling Process, I can use my ideas to manually pull the cables. After the cabling is finished, the software can help me adjust the cables automatically from these two aspects. Or, even if it has been deprecated, if you want to change the line, it is also a rough change, and then let the software adjust. Even in the end, I felt that I needed to adjust the package of components. That is to say, the whole piece of wiring had to be adjusted and all the software had to do it. That would be much faster. I use protel98. I know that this software can automatically and uniformly adjust the distance of the component encapsulation without automatically adjusting the line distance and line width. It may be that some of these functions are not available yet, or there are other ways to do so. Please refer to them here.
Answer: line width and line distance are two important factors that affect the line density. Generally, when designing a plate with a high operating frequency, the characteristic impedance of the cabling needs to be determined before wiring. When the PCB layout is fixed, the characteristic impedance determines the line width. The line distance is absolutely related to the crosstalk size. The minimum acceptable line distance determines whether the effect of crosstalk on the Signal Time Delay and signal integrity is acceptable. The minimum line distance can be obtained by the simulation software pre-simulation. That is to say, before wiring, the required line width and minimum line distance should have been determined and cannot be changed at will, because it will affect the characteristic impedance and crosstalk. This is also the reason why most EDA cabling software does not rotate the wire width and the minimum line distance during Automatic cabling or adjustment. If this line width and minimum line distance have been set for the cabling software, the convenience of wiring adjustment depends on the capability of the software winding engine. If you are interested in the company dition, refer to our winding engine,

15. about high-speed digital PCB
What is the principle of selecting the grounding point between the PCB and the housing? In addition, general PCB layout engineers always follow the Design Guide/layout guideline. Do I want to know whether Hardware/System engineers or senior PCB engineers are generally working on the guide? Who should be primarily responsible for the performance of the board-level system. Thank you!
Answer: The principle of selection of grounding points with the shell is to use chassis ground to provide a low impedance path to the reflux current (returning current) and to control the reflux current path. For example, in the vicinity of a high-frequency device or clock generator, a fixed screw can be used to connect the PCB formation to the chassis ground to minimize the entire current loop area and reduce electromagnetic radiation. Who should be responsible for developing guideline? Maybe every company has different situations and different arrangements. The establishment of guideline must have a full understanding of the entire system, Chip, circuit operation principle, in order to develop a guideline that conforms to electrical specifications and can be implemented. Therefore, in my personal opinion, Hardware System Engineers seem to be more suitable for this role. Of course, Senior PCB engineers can provide real-time experience, so that the guideline can be better implemented.

16. The circuit board debug should start from those aspects.
Q: I would like to ask if the Board is well designed and produced. The debugging should start from those aspects.
A: In terms of digital circuits, we should first determine three things in sequence:
1. confirm that all power values meet the design requirements. Some systems with multiple power supplies may require a certain specification for the order and speed of power supply.
2. confirm that all clock frequencies are working normally and there is no non-monotonous (non-monotonic) Problem on the signal edge.
3. Check whether the reset signal meets the standard requirements.
If these are all normal, the chip should signal the first cycle (cycle. Next, debug based on the system operating principle and bus protocol.

17. How can the commonly used electronic PCB design software meet the Circuit Anti-interference requirements?
Q: What PCB design software are available now? How can we use protel99 to reasonably design a PCB that meets our own requirements? For example, how can we meet the requirements of high-frequency circuits and how can we consider the circuit to meet anti-interference requirements?
A: I have no experience in using PROTEL. I will only discuss the design principles below.
High-frequency digital circuits mainly consider the influence of Transmission Line effects on signal quality and timing (timing. Such as continuous and matching of Characteristic Impedance, selection of end connection mode, selection of topology mode, line length and spacing, and control of clock (or strobe) signal skew.
If the device is fixed, the general anti-interference method is to increase the gap or add ground guard traces.

17. How can the commonly used electronic PCB design software meet the Circuit Anti-interference requirements?
Q: What PCB design software are available now? How can we use protel99 to reasonably design a PCB that meets our own requirements? For example, how can we meet the requirements of high-frequency circuits and how can we consider the circuit to meet anti-interference requirements?
A: I have no experience in using PROTEL. I will only discuss the design principles below.
High-frequency digital circuits mainly consider the influence of Transmission Line effects on signal quality and timing (timing. Such as continuous and matching of Characteristic Impedance, selection of end connection mode, selection of topology mode, line length and spacing, and control of clock (or strobe) signal skew.
If the device is fixed, the general anti-interference method is to increase the gap or add ground guard traces.

18. Wiring of LVDS Signals
Q: In principle, LVDS low-voltage differential signals are long and parallel cables, but in fact they are difficult to implement. Can we provide some experience?
Answer: due to the long and parallel requirements for differential signal cabling, there are the following reasons:
1. The purpose of parallelism is to ensure the integrity of the differential impedance. Where the horizontal distance is different, the difference impedance is not continuous.
2. The purpose of equality is to ensure the accuracy and symmetry of time series (timing. Because the timing of the differential signal is related to the intersection of the two signals (or the relative voltage difference), if the difference is not long, the intersection will not appear in the center of the amplitude of the signal (swing amplitude, it will also cause asymmetry between two adjacent time intervals, which increases the difficulty of time series control.
3. Unequal lengths also increase the components of common mode signals, affecting signal integrity (signal integrity ).

19: Q: When the PCB size is fixed, if more functions need to be accommodated in the design, the PCB cabling density needs to be improved, however, this may lead to enhanced interference between the cabling and the impedance cannot be reduced due to excessive cabling. Please ask experts to introduce their skills in high-speed (> 100 MHz) high-density PCB design?
A: When designing high-speed and high-density PCB, crosstalk interference must pay special attention to it, because it is used for timing and signal integrity) it has a huge impact. Note the following:
1. Control the continuity and matching of the line characteristics impedance.
2. The size of the padding. Generally, the spacing is twice the line width. Through simulation, we can know the influence of cabling Spacing on timing sequence and signal integrity, and find the tolerable minimum spacing. Different chip signals may have different results.
3. select an appropriate connection method.
4. Avoid having the same line direction between the upper and lower adjacent two layers, or even overlap them up and down, because the crosstalk is larger than the adjacent line of the same layer.
5. Use blind buried holes (blind/buried via) to increase the cabling area. However, PCB production costs will increase.
In actual execution, it is really difficult to achieve full parallelism and equality, but we still need to do it as much as possible. In addition, differential and common-mode connections can be reserved to mitigate the impact on timing and signal integrity.

20. Power Supply Filtering
Q: The LC circuit is often used for filtering analog power supply. However, I found that LC sometimes has a poor filtering effect than RC. Why? What is the filtering method of inductance and capacitance?
Answer: when comparing the filtering effects of LC and RC, you must consider whether the selection of the frequency band and Inductance Value to be filtered out is appropriate. Because the inductance's reactance size is related to the Inductance Value and frequency. If the noise frequency of the power supply is low and the inductance value is not large enough, the filtering effect may be inferior to that of RC. However, the cost of using RC filters is that the resistance consumes energy and is less efficient. Pay attention to the power that the selected resistance can withstand.
In addition to the noise frequency to be filtered out, the selection of the inductance value also considers the reaction capability of the instantaneous current. If the output end of LC has a chance to generate a large current instantly, the inductance value will be too high to impede the speed at which the large current flows through the inductance and increase ripple noise ).
The capacitance value is related to the size of the pattern noise standard value that can be tolerated. The smaller the ripple noise value, the larger the capacitance value. The capacitor's ESR/ESL also has an impact.
In addition, if this LC is placed at the output end of the switching regulation power, pay attention to the Pole zero (pole/zero) generated by this LC) influence on negative feedback control loop stability.

21. Multi-number/mode connection
Q: When multiple number/module functional blocks exist in a PCB, the general practice is to separate the number/module and connect them at one point. In this way, the ground on a PCB Board will be divided into multiple blocks, and how to connect them is also a major problem. However, some people adopt another method, that is, to ensure that the number/module is separated and that the number/module signal does not cross each other, the entire PCB is not separated, the number/mode ground is connected to the ground plane. Please advise if you do so.
Answer: The reason for separating the number/mode is that the digital circuit will generate noise between the power supply and the ground during the high/low potential switching. The noise size is related to the signal speed and current size. If the ground plane is not split and the noise produced by the digital area circuit is large, and the analog area circuit is very close, even if the digital signal is not crossover, the analog signal will still be disturbed by ground noise. That is to say, the Digital-to-ground approach can only be used when the analog circuit area is far away from the digital circuit area that generates large noise. In addition, the requirement that the digital signal line cannot be crossed is that the return current path (return current path) of a digital signal with a higher speed will try to stream back to the source of the digital signal near the bottom of the line, if the digital-analog signal is crossed, the noise generated by the returned current appears in the analog circuit area.

22. circuit board design and EMC!
Q: If EMC is taken into account in circuit board design, it will definitely increase a lot of costs. How can I answer EMC's requirements as much as possible without bringing too much cost pressure? Thank you.
A: The cost of EMC increase on PCB is usually due to increasing the number of layers to enhance the shielding effect and increasing Ferrite Bead and choke to suppress high-frequency harmonic devices. In addition, it is usually necessary to match the shield structure on other organizations to make the entire system pass the EMC requirements. The following provides only a few electromagnetic radiation effects on the PCB design techniques to reduce the circuit generation.
1. Use a device with a low signal slope (slew rate) as much as possible to reduce the high-frequency components produced by the signal. 2. Pay attention to the placement of high-frequency devices. Do not be too close to external connectors.
3. Pay attention to the impedance matching of High-speed signals. The Strip layer and return current path can reduce high-frequency reflection and radiation.
4. Place enough uncoupled capacitors on the power pins of each device to ease noise on the power supply layer and formation. Pay special attention to the frequency response and Temperature Characteristics of the capacitor to meet the design requirements.
5. the ground near the external connector can be properly separated from the ground layer, and the ground near the connector is connected to the chassis ground.
6. You can use ground guard/shunt traces to handle high-speed signals. However, pay attention to the impact of guard/shunt traces on the impedance of the Strip characteristics.
7. The power supply layer is 20 h longer than the formation, and h indicates the distance between the power supply layer and the formation.

23. GSM mobile phone PCB design
Q: Do you have any requirements and skills for designing GSM mobile phone PCB?
A: The Challenges of mobile phone PCB design are: Small board area and RF circuit. Because the available board area is limited, and there are several different circuit areas, such as RF circuit, power circuit, voice analog circuit, General Digital Circuit, etc, they all have different design requirements.
1. First, the RF and non-RF circuits must be properly separated on the board. Because the RF power supply, ground, and impedance design specifications are strict.
2. Because the board area is small, blind buried holes (blind/buried via) may be required to increase the Strip area.
3. Do not use other digital circuits or RF circuits to produce crosstalk. In addition to widening the Strip distance, you can also use ground guard trace to suppress crosstalk.
4. Proper ground separation, especially when simulating a circuit, should be paid special attention not to be disturbed by the ground noise of other circuits.
5. Pay attention to the return current path of signals in each circuit area to avoid increasing the possibility of crosstalk.

24: what issues should I pay attention to during PCB design?
Answer: The issues that need to be paid attention to during PCB design vary with the application products. Just as the attention of digital and analog circuits varies. The following are just a few general principles to pay attention.
1. Determine the PCB stack, including the arrangement of the power supply layer, formation layer, and cabling layer, and the cabling direction of each cabling layer. These will affect the signal quality and even electromagnetic radiation problems.
2. Power Supply and location-related cabling and passing holes (VIA) should be as wide as possible and as large as possible.
3. Regional configuration of different characteristic circuits. Good region configuration has a great relationship with the difficulty of cabling and even the signal quality.
4. Design Rule check and test-related design (such as test points) should be configured with the manufacturing process of the production plant ). Other electrical-related problems are absolutely related to the circuit characteristics. For example, even if they are all digital circuits, the characteristic impedance of the cabling depends on the speed and length of the circuit.

24: what issues should I pay attention to during PCB design?
Answer: The issues that need to be paid attention to during PCB design vary with the application products. Just as the attention of digital and analog circuits varies. The following are just a few general principles to pay attention.
1. Determine the PCB stack, including the arrangement of the power supply layer, formation layer, and cabling layer, and the cabling direction of each cabling layer. These will affect the signal quality and even electromagnetic radiation problems.
2. Power Supply and location-related cabling and passing holes (VIA) should be as wide as possible and as large as possible.
3. Regional configuration of different characteristic circuits. Good region configuration has a great relationship with the difficulty of cabling and even the signal quality.
4. Design Rule check and test-related design (such as test points) should be configured with the manufacturing process of the production plant ). Other electrical-related problems are absolutely related to the circuit characteristics. For example, even if they are all digital circuits, the characteristic impedance of the cabling depends on the speed and length of the circuit.

25. EMC and EMI Problems in High-Speed PCB design
Q: During High-Speed PCB design, all the software we use is to check the configured EMC and EMI rules, designers should consider EMC and EMI rules from those aspects. How should we set rules? I am using Cadence software.
A: Generally, both radiated and conducting need to be considered during EMI/EMC design. the former belongs to the higher part (> 30 MHz) and the latter is the lower part (<30 MHz ). therefore, you cannot only pay attention to the high frequency and ignore the low frequency.
A good EMI/EMC design must take into account the device location, PCB layout, online cabling, and device selection at the beginning, if there is no better arrangement in advance, solving the problem afterwards will be more than half the effort and increase the cost. for example, the location of the clock generator should not be close to the external connector as much as possible, and the high-speed signal should go through the inner layer as much as possible and pay attention to the continuous feature impedance matching and reference layer to reduce reflection, the signal slope (slew rate) pushed by the device is as small as possible to reduce the high-frequency components. When selecting a decoupling/bypass capacitor, pay attention to whether the frequency response meets the requirement to reduce the noise on the power supply layer. in addition, pay attention to the reflux path of high-frequency signal current so that the loop area is as small as possible (that is, the loop impedance is as small as possible) to reduce radiation. it can also be used to divide the formation to control the range of high-frequency noise. finally, select the PCB and shell grounding point (chassis ground ).

26. Impedance Matching in PCB design
Q: In high-speed PCB design, impedance matching must be considered to prevent reflection. However, because the PCB processing technology limits the continuity of impedance, simulation cannot be performed, how should we consider this issue during schematic design? In addition, I do not know where to provide a more accurate IBIS model library. Most of the databases we download from the Internet are inaccurate, which affects the reference of simulation.
A: impedance matching is one of the design elements when designing high-speed PCB circuits. The impedance value has an absolute relationship with the cabling method, for example, the distance between the walking surface layer (microstrip) or the inner layer (stripline/Double stripline) and the reference layer (Power layer or ground layer, the strip width and PCB Material affect the characteristic impedance of the Strip. That is to say, the impedance value can be determined only after wiring. Generally, the simulation software cannot consider some discontinuous impedance cabling due to the limitations of the line model or the mathematical algorithm used. At this time, only some Terminators can be reserved in the schematic diagram ), such as series resistance, to ease the effect of non-consecutive line impedance. The fundamental solution to the problem is to avoid the occurrence of non-consecutive impedance during cabling.
The accuracy of the IBIS model directly affects the simulation results. Basically, IBIS can be regarded as the electrical characteristic data of the actual chip I/O buffer equivalent circuit. Generally, it can be converted from the Spice Model (measurement can also be used, but there are many restrictions ), however, spice data is absolutely related to chip manufacturing. Therefore, spice data is different for different chip manufacturers of the same device, then, the data in the transformed IBIS model also changes accordingly. That is to say, If Vendor A's devices are used, only they have the ability to provide accurate model information for their devices, because no one else knows more about the process by which their devices are made. If the IBIS provided by the vendor is not accurate, it is the fundamental solution to constantly ask the vendor for improvement.

27. Comparison of PCB design tools
Q: from your personal point of view: For analog circuits (microwave, high frequency, low frequency), Digital Circuits (microwave, high frequency, low frequency) analog and digital hybrid circuits (microwave, high frequency, low frequency). Which EDA tool is designed for PCB )? Can you separately describe.
A: Due to my application understanding, I cannot thoroughly compare the performance and price ratio of EDA tools. To select software based on the scope of application, the principle I advocate is sufficient.
Conventional Circuit Design, innoveda pads is very good, and there is a combination of simulation software, and this type of design often occupies 70% of the application scenarios. In high-speed circuit design, analog and digital hybrid circuits, the cadence solution should belong to software with good performance and price. Of course, the performance of mentor is still very good, in particular, it should be the best in design process management.
The above points are purely personal opinions!

28. Separated layout and intelligent layout of data/Mode
Q: When a system has both small RF signals and high-speed clock signals, we usually adopt separate data/mode layout to reduce electromagnetic interference through physical isolation and filtering, however, this is of course unfavorable for miniaturization, high integration, and reduction of structure processing costs, and the effect is still not necessarily satisfactory, because no matter whether it is a digital grounding or a simulated grounding point, it will eventually be connected to the shell, as a result, interference is coupled to the front end through grounding, which is a headache for us. I would like to ask experts for such measures.
A: There are both low RF signals and high-speed clock signals. The reasons for interference need to be carefully analyzed and different solutions should be used accordingly. Based on the specific application, you can try the following methods.
0: there is a small RF signal, high-speed clock signal, the first is to separate the power supply, should not use switching power supply, you can choose a linear power supply.
1: select a small RF signal, one of the high-speed clock signals. The connection adopts a shielded cable.
2: connect the digital grounding point to the power source ground (requiring better isolation of power supply), simulate grounding point to the chassis ground.
3: Try to remove interference by filtering.