Naming Convention for aveon signal type (IC design) (FPGA builder)

 

1 Module my_multiport_component (
2 // Signals for aveon-mm slave port "S1"
3 Avs_s1_clk,
4 Avs_s1_reset_n,
5 Avs_s1_address,
6 Avs_s1_read,
7 Avs_s1_write,
8 Avs_s1_writedata,
9 Avs_s1_readdata,
10 Avs_s1_export_dac_output,
11 // Signals for aveon-mm slave port "S2"
12 Avs_s2_address,
13 Avs_s2_read,
14 Avs_s2_readdata,
15 Avs_s2_export_dac_output,
16 // Clock/Reset Interface
17 Csi_clockreset_clk
18 );

See also
(Dynamic Route) New Alibaba version of aveon interface (SOC) (FPGA builder)
(Formerly known as the benchmark) in-depth exploration of the checksum master slave instance (SOC) (FPGA builder) (nio ii) (de2) of Altera)

Reference
Quartus II version 7.2 handbook volumn 4: Systems builder P.5-4