Research on Windows CE embedded Navigation System (Hardware Design 3)

1.1 flash interface circuit design

Flash memory is a kind of memory in-system (in-system) for electrical erasure. After power loss, information will not be lost. It features low power consumption, large capacity, fast write/Erase speed, full or split-sector programming and erasure. Chip operations are completed by internal embedded algorithms, which are widely used in various embedded systems. The two main non-easy-to-lose flash technologies on the market are nor and NAND. Nor is executed in the chip, so that the application can run directly in Flash without having to read the code into the system Ram. Nor transmission efficiency is very high, in 1 ~ 4 MB of small capacity has a high cost efficiency, but the low write and erase speed greatly affects its performance. The NAND structure provides a very high unit density, achieves a high storage density, and writes and erases quickly. The difficulty of using NAND lies in Flash management and special system interfaces. NAND Flash does not adopt the random read Technology of memory. It reads a block at a time, usually 512 bytes at a time. Because the code on NAND Flash cannot be directly run, apart from using NAND Flash, a small nor flash is usually added to run the startup code.

In combination with the respective features of nor flash and NAND Flash, the system has extended a 32 m × 16 bit (which can be expanded to m × 16 bit, which can use the U3 circuit) the NAND flash chip k9f1216u0a and a 512k × 16bit nor flash chip am29lv160db can guide the system startup through jumpers to ensure reliable running of the startup code. As shown in Figure 3.8, the line selection/cs of nor flash is connected to the ngcs0 pin, and the data bus data of s3c2440a [15 .. 0] data bus connecting the nor flash chip d [15 .. 0], address bus ADDR [22 .. 1] a [21 .. 0] pin. Nor flash chip write enabling pin/we connect to the nwe pin of s3c2440a chip, NAND Flash, nor flash circuit diagram 4.8, figure 4.9, figure 4.10.

Figure 4.8 NAND Flash circuit diagram

Figure 4.9 expanded NAND Flash circuit diagram

Figure 4.10 Nor flash circuit diagram

1.2 audio interface circuit design

The embedded IIS Bus Controller of s3c2440a implements an external 8/16-bit stereo audio codec IC interface. It can also provide DMA transmission mode rather than interrupt mode for the FIFO channel, in this way, both the IIS bus data format and MSB-justified data format can be used to send and receive data simultaneously. It is easy to extend the audio interface. You only need to connect the Audio Codec Chip to the Digital Audio bus.

IIS (Inter-IC Sound Bus, built-in integrated circuit Audio bus) bus is a serial Digital Audio bus protocol proposed by Philips. It is a multimedia-oriented Audio bus dedicated to data transmission between audio devices, providing sequential connections to standard codecs for digital stereo. IIS bus only processes sound data, and other signals (such as control signals) must be transmitted separately. To minimize the number of circuit leads, IIS only uses three serial buses: provides time-sharing data lines, field selection lines, and clock signal lines.

The audio chip uses the uda1341ts of Philips and is directly connected to the IIS pin of S3C2410 in 4.11. The chip also provides standard L3, microphone, and speaker interfaces. The L3 interface pins are connected to the three gpio output pins of S3C2440 respectively, and the L3 interface is controlled through gpio. The uda1341ts audio chip integrates digital audio and mixer functions. The digital audio function can play a digital sound or recording sound. The mixer is used to control the volume of various inputs/outputs, and is controlled through the L3 interface.

Figure 4.11 audio interface circuit

1.3 serial port Circuit Design

The serial port is a commonly used interface of a computer and has the characteristics of few connections and simple communication. Serial Port technology is now mature and stable, and is widely used in the interconnection between various devices. The most widely used 9-pin serial port is now. The pin function is shown in table 1.

Table 1 DB-9 Serial Port Pin Function

Pin	Function
1	Carrier Detection (DCD)
2	Receive (rxd)
3	Send (txd)
4	Data Terminal ready (DTR)
5	Signal Location (Gnd)
6	Data ready (DSR)
7	Send request (RTS)
8	Clear sending (CTS)
9	Zhenling detection (RI)

S3c2440a has a built-in serial port transceiver module. As long as the serial port level conversion circuit is designed in the peripheral module, it can communicate with other devices in a serial way. In this system, the sp3232een level conversion chip is used, one-to-one serial port signal level conversion, as shown in 4.12.

Figure 4.12 serial port Circuit

1.4 USB Interface Circuit

USB (Universal Serial Bus) is a fast and flexible bus interface. In addition to the physical layer and electrical layer standards for communications, the USB standard also defines a relatively complete set of software protocol stacks, which makes it easy for most USB devices to work on various platforms. As a high-speed bus interface, USB is suitable for multiple devices and supports hot swapping. All configuration processes are automatically completed by the system without user intervention. Figure 4.13 shows the circuit diagram of the system, which consists of host and device.

Figure 4.13 USB circuit diagram

1.5 gpio Interface Circuit

General purpose IO Interface (gpio) is a very important I/O interface in the arm system and on-chip SOC (System-on-chip) systems, it has the advantages of flexible use, good configurability, and low hardware cost, and is widely used in arm systems. Gpio is not only practical, but also powerful, mainly including the following six functions.

L General I/O (gpio): the most basic function, which can drive led, generate PWM, and drive buzzer.

L External Interrupt/wake-up line: when the port must be configured in input mode, all ports have external interrupt capabilities.

L reuse function (AF): the port of the reuse function has both Io functions. During the reset period and after the reset, the reuse function is not enabled, and the I/O port is configured as the float input mode: (cnfx [1:0] = 01b, modex [1:0] = 00b ).

L software re- ing I/O reuse function: To optimize the number of peripheral I/O functions encapsulated by different devices, some reuse functions can be re-mapped to other devices. This can be done by configuring the corresponding registers in the software. In this case, the reuse function is no longer mapped to their original pins.

Figure 4.14 gpio circuit diagram

To facilitate user expansion, the system also integrates gpio components for mode selection, led control, interrupt wake-up, I2C read/write, and other functions. Gpio circuit diagram 4.14.