Rambus New technology: 5 nanosecond speed Memory switch

Rambus is notorious, but it does have a set of skills. At the 2011-Year VLSI Symposium in Tokyo, Rambus announced a groundbreaking, fast-power, low-power clock technology that is expected to bring a new face to memory devices.

With 40nm low-power http://www.aliyun.com/zixun/aggregation/19282.html ">cmos process, this new technology allows for within 0.5 nanosecond time to complete from zero power standby to each differential link 5+ Gbps High speed data transmission working state conversion, while running power consumption is only 2.4mw/gb/s, that is, full speed work at the time of 12mW per second.

To improve the efficiency of servers and mobile systems, people have been looking for ways to reduce the power of the memory subsystem. The main challenge in server application is to quickly cut in and out the minimum power state, while the mobile system supports a variety of power state, but low-power operation usually requires a complex power state circuit to match.

Rambus claims that the new technologies they have developed can avoid these drawbacks, enable the memory subsystem to switch very quickly, and integrate with Soc and memory interfaces, SOC and SOC connections, thereby shortening access latency, simplifying system design, and reducing overall system power consumption.

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